Processing Lane Defect Detection via Partial Redundancy
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Solution Overview
Problem
Existing defect detection methods for electronic devices using system semiconductors degrade performance and increase power consumption by activating multiple logics simultaneously or requiring test workloads at regular intervals, leading to challenges in securing high test coverage.
Innovation Solution
An electronic device with additional processing lanes and a controller identifies lane groups for identical input data processing, compares processing results, and detects defects without deactivating the entire system, using partial redundancy to maintain performance and minimize hardware area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a built-in self-test method using a scan chain in logic is used to detect defects, then defect detection capability is improved, but power consumption increases and performance degrades due to activating multiple logics simultaneously
Solution Approach 1:
The processor is divided into multiple processing lanes (first processing lane and second processing lane) that can operate independently. During defect detection, only the necessary lanes are activated to perform comparison operations, rather than activating all logics simultaneously. This segmentation allows defect detection to be performed with minimal power consumption while maintaining detection capability.
Solution Approach 2:
The patent uses an additional processing lane as a copy of the functional units in existing lanes to perform comparison operations. This additional lane is specifically designed for defect detection purposes, allowing the system to detect defects by comparing results from multiple lanes without requiring full activation of all processing logics, thereby reducing power consumption.
2Reliability
If test workloads are executed at regular intervals to detect defects, then defect detection coverage is improved, but system performance degrades due to frequent testing interruptions
Solution Approach 1:
The defect detection mechanism operates continuously in the background by comparing results from multiple processing lanes as they naturally execute workloads. The comparison operation is performed continuously without interrupting the normal workflow, allowing defect detection to occur alongside productive work rather than requiring separate test intervals that would degrade system performance.
Solution Approach 2:
The processing lanes serve dual functions: they perform normal computational tasks during regular operation and simultaneously perform defect detection through comparison operations. This multi-functionality eliminates the need for separate dedicated test workloads, as the same processing infrastructure is used for both productive work and defect detection, maintaining system performance while achieving high test coverage.
3Reliability
If multiple logics are activated simultaneously for defect detection, then test coverage is improved, but hardware area increases due to the need for additional redundant components
Solution Approach 1:
Instead of activating all processing lanes for defect detection, the patent uses a selective approach where only the necessary number of lanes are activated based on the specific detection needs. The system can dynamically adjust the number of active lanes, using partial action to achieve sufficient test coverage without requiring all possible redundant components to be active simultaneously, thereby reducing hardware area requirements.
Data Source
AI summary
The present disclosure relates to an electronic device for performing a defect detection and an operation method thereof, and an operation method of an electronic device including a plurality of processing lanes and at least one additional processing lane according to an example embodiment of the present disclosure includes identifying a lane group including lanes to process identical input data among a plurality of lanes including the plurality of processing lanes and the at least one additional processing lane, identifying, for each of a plurality of lane groups, comparison result data indicating a result of comparison between processing result data of lanes included in each lane group, and detecting whether a defect occurs for at least one of the plurality of lanes based on the comparison result data of the plurality of lane groups.