Multi-Lane Optical Transceiver Lane Drop Detection With Shared PLL Switching

Solution Overview

Problem

Multi-lane optical transceivers face challenges in maintaining high data rates and power efficiency due to the use of per lane phase interpolators and phase-locked loops, which consume significant area and power, and require seamless lane switching without affecting active channels.

Innovation Solution

Implement a fast digital lane drop detection system that monitors lane validity and dynamically switches the master lane using a 'difference-of-the-difference' technique, reducing the number of phase interpolators and allowing seamless lane switching with a single PLL/PPM master architecture.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If per lane phase interpolators and phase-locked loops are used for each transmitter and receiver block, then frequency information transfer is achieved, but area and power consumption increase significantly

Engineering Contradiction:

Improvefrequency information transferVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent merges the phase interpolator and phase-locked loop functions into a shared resource that serves multiple lanes. Instead of having dedicated PIs and PLLs for each lane, a single PLL/PPM master architecture provides frequency information to all lanes, significantly reducing power consumption while maintaining the required frequency transfer reliability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared PLL/PPM master is designed to serve multiple lanes universally. The system can dynamically allocate this shared resource to different lanes based on active channel requirements, allowing the same hardware to perform the frequency information transfer function for any lane without requiring dedicated per-lane components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If per lane phase interpolators and phase-locked loops are used, then frequency information transfer is achieved, but device area increases

Engineering Contradiction:

Improvefrequency information transferVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the phase interpolator and phase-locked loop functions into a shared resource that serves multiple lanes. Instead of having dedicated PIs and PLLs for each lane, a single PLL/PPM master architecture provides frequency information to all lanes, significantly reducing power consumption while maintaining the required frequency transfer reliability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared PLL/PPM master is designed to serve multiple lanes universally. The system can dynamically allocate this shared resource to different lanes based on active channel requirements, allowing the same hardware to perform the frequency information transfer function for any lane without requiring dedicated per-lane components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If dynamic lane switching is implemented, then adaptability is improved, but system complexity increases

Engineering Contradiction:

Improvelane switching capabilityVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system implements dynamic lane switching capability where the active lane can be changed on the fly without affecting other channels. The PLL/PPM master can be rapidly reconfigured to serve different lanes by updating control parameters, enabling adaptive response to lane drops or failures while maintaining a relatively simple underlying architecture through the use of a single shared resource rather than multiple fixed assignments.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250294271A1Fast digital lane drop detection system for multi-lane direct detect transceivers

Publication Date: 2025.09.18 CISCO TECHNOLOGY INC

AI summary

Lane drop detection techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing a phase interpolator (PI) control word for each lane of an optical transceiver; determining a lane difference between a master lane and each non-master lane; calculating a difference associated with each non-master lane, wherein the difference associated with a given non-master lane is calculated as a difference between the lane difference associated with the given non-master lane and a reference lane difference associated with the given non-master lane; upon determining that at least one of the differences has reached a drift threshold, determining that the master lane or one or more of the non-master lanes is invalid based on which of the differences have reached the drift threshold; and performing a control action when the master lane or one or more of the non-master lanes is invalid.