Lane Position Information for Vector Processing
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Solution Overview
Problem
Floating-point arithmetic is non-associative, leading to reproducibility issues and inefficiencies in parallel processing due to rounding and normalization, making it difficult to achieve consistent results when adding or subtracting numbers in a different order.
Innovation Solution
The use of Redundant High-Precision Anchor (RHPA) representation, which allows for fast and correct accumulation of floating-point numbers by representing values in a redundant format with overlapping significance bits, enabling parallel processing without the need for rounding or normalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If floating-point arithmetic is performed using standard rounding and normalization, then calculation speed is improved through parallel processing, but result reproducibility deteriorates due to non-associative operations
Solution Approach 1:
The patent segments the floating-point number into multiple components (significand bits and exponent bits) that are processed separately through different lanes. Each lane processes specific bits in parallel without requiring traditional rounding and normalization, thereby maintaining both high calculation speed and result reproducibility.
Solution Approach 2:
The patent introduces a new dimension by processing floating-point numbers in a component-wise manner across multiple lanes rather than as complete numbers. This dimensional change allows parallel processing of significand and exponent bits independently, eliminating the non-associative rounding operations while preserving computational accuracy.
2Reliability
If floating-point additions are performed sequentially to ensure reproducible results, then result reproducibility is improved, but calculation speed deteriorates
Solution Approach 1:
The patent divides the floating-point addition operation into segmented lane processing where each lane handles specific bit components. This segmentation enables parallel execution of multiple additions simultaneously while maintaining reproducible results through consistent lane position information tracking.
Solution Approach 2:
The patent performs preliminary identification of lane position information before executing parallel additions. By pre-establishing the positional relationships and processing order of different lanes, the system ensures reproducible results are achieved through the parallel operations without requiring sequential execution.
3Measurement precision
If redundant high-precision anchor representation is used with overlapping significance bits, then calculation accuracy is improved and parallel processing is enabled, but data structure complexity increases
Solution Approach 1:
The patent creates a universal data representation format where the redundant high-precision anchor structure serves multiple functions: it provides high calculation accuracy through overlapping significance bits, enables parallel processing through lane segmentation, and maintains manageable complexity through systematic bit allocation rules that can be applied consistently across different operations.
Data Source
AI summary
Processing circuitry performs a plurality of lanes of processing on respective data elements of at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry identifies lane position information for each lane of processing, the lane position information for a given lane identifying a relative position of the corresponding result data element to be generated by the given lane within a corresponding result data value spanning one or more result data elements of the result vector. The processing circuitry is configured to perform each lane of processing in dependence on the lane position information identified for that lane. This enables generation of results which are wider or narrower than the vector size supported in hardware.