Large Display Touch Sensor Segmentation
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Solution Overview
Problem
Capacitive touch panels with a single ITO layer (SITO) face limitations in scalability due to pin constraints, making them unsuitable for large-size displays, while maintaining lower costs and fewer IC requirements.
Innovation Solution
A touch sensor design featuring a substrate with two areas, each with a group of conductive patterns connected to separate processors, allowing for efficient detection of touch points across a larger surface area by distributing conductive patterns and processors effectively, even with fewer pins than total patterns, enabling application on displays larger than 7 inches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single ITO layer with one IC is used (SITO panel), then material cost and manufacturing cost are reduced, but the number of pins on the IC becomes insufficient for large size displays
Solution Approach 1:
The patent divides the touch sensor into multiple regions (first area and second area) with separate conductive pattern groups (first group and second group). Each group is independently connected to processing circuits, allowing the system to scale to large displays without requiring a single IC with excessive pins. This segmentation enables modular expansion while maintaining cost-effectiveness.
2Adaptability or versatility
If multiple ITO layers are used (DITO panel), then the number of pins required is reduced per IC, but material cost and manufacturing complexity increase
Solution Approach 1:
Instead of using multiple ITO layers, the patent segments the conductive patterns into multiple groups on a single ITO layer. This approach achieves pin compatibility for large displays while avoiding the increased material costs and manufacturing complexity associated with multiple ITO layers.
3Measurement precision
If conductive patterns are distributed across large area, then coverage and detection accuracy improve, but the number of pins required exceeds IC capacity
Solution Approach 1:
The patent segments the conductive patterns into multiple groups that can be independently processed. This allows comprehensive coverage of large display areas with high detection accuracy while keeping the pin count per IC manageable through regional processing assignments.
Solution Approach 2:
The patent introduces a spatial dimension to the processing architecture by assigning different regions of the touch sensor to different processing circuits. This dimensional organization allows the system to handle large numbers of conductive patterns without proportionally increasing IC pin requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables cost-effective, large-size capacitive touch sensors by ensuring that each processor connects sufficient conductive patterns, enhancing accuracy and response time, thus overcoming the pin constraint limitations of SITO panels.
Implementation Method 1
The capacitive touch panel utilizes the current induced by the capacitance variation, because of the capacitance varied with the static electricity between the human body and the transparent electrode, to locate the touch point of the human body.
Data Source
AI summary
A touch sensor includes a substrate, a touch sensing layer, a first processor and a second processor. The substrate includes a first area and a second area. The first area and the second area are on the same surface of the substrate. The touch sensing layer is disposed on the substrate, and includes a first group of conductive patterns and a second group of conductive patterns. The first group of conductive patterns is disposed on the first area, and includes a plurality of first conductive patterns. The second group of conductive patterns is disposed on the second area, and includes a plurality of second conductive patterns. The first processor is electrically connected to the first conductive patterns. The second processor is electrically connected to the second conductive patterns.