Large Grain Conductive Structure for Narrow Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor interconnect structures face high electrical resistivity and low electromigration resistance due to small grain sizes in conductive features, especially below 75 nm, leading to increased grain boundary scattering and reduced performance.
Innovation Solution
A method is developed to form interconnect structures with a bamboo microstructure and large grain size by using a grain growth promotion layer, agglomerated plating seed layer, and subsequent anneals to enhance grain growth within the conductive material, resulting in a conductive structure with an average grain size greater than 0.05 microns and improved crystal orientation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plating and deposition processes are used to form conductive features, then the manufacturing process is simple and straightforward, but the resulting conductive structures have small grain sizes (0.02 microns or less) leading to high electrical resistivity and increased grain boundary scattering
Solution Approach 1:
A grain growth promotion layer is deposited prior to the conductive material as a preliminary action to facilitate subsequent grain growth. This layer is specifically designed to promote grain boundary motion and enable grain growth during annealing processes, thereby achieving large grain sizes in the final conductive structure without requiring complex in-situ grain growth equipment.
Solution Approach 2:
The invention employs annealing processes that change temperature and time parameters to induce grain growth. By controlling annealing temperature, duration, and atmosphere, the conductive material transforms from a fine-grained structure to a large-grain structure, reducing grain boundary scattering and electrical resistivity while maintaining the conductive functionality.
2Ease of manufacture
If small grain size conductive material is used in narrow interconnect openings, then the manufacturing process is easier, but the electrical resistivity increases significantly due to grain boundary scattering
Solution Approach 1:
The grain growth promotion layer is selectively applied only within the interconnect openings and contact holes where grain growth is needed. This localized approach enables large grain formation in critical conductive regions while maintaining manufacturing simplicity, thereby reducing electrical resistivity without complicating the overall fabrication process.
3Manufacturing precision
If conventional annealing is performed after deposition, then the conductive material is formed, but grain growth is limited because grain boundary motion from the overburden does not extend down into small features
Solution Approach 1:
The grain growth promotion layer acts as an intermediary between the deposited conductive material and the underlying structure. This intermediate layer facilitates grain boundary motion and enables grain growth to propagate downward into small interconnect features, overcoming the limitation of conventional annealing where grain boundaries cannot effectively move in narrow structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach significantly reduces electrical resistance and enhances electromigration resistance, leading to improved signal transmission and circuit reliability, with conductive structures exhibiting 10-30% lower electron scattering and resistance compared to prior art.
Implementation Method 1
a subsequent second anneal that causes grain growth of the metal-containing conductive material
Implementation Method 2
The first anneal is performed under conditions that cause agglomeration of a deposited plating seed layer within the at least one opening
Implementation Method 3
a conductive structure is formed within the at least one opening. The conductive structure is formed by deposition of a metal-containing conductive material
Implementation Method 4
The first anneal is performed under conditions that cause agglomeration of a deposited plating seed layer within the at least one opening
Data Source
AI summary
An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer, a grain growth promotion layer, an agglomerated plating seed layer, an optional second plating seed layer a conductive structure. The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.