Large IC Die Stitching for Multi-Photomask Wafer-Scale Integration
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Solution Overview
Problem
Conventional photolithographic techniques for high-volume manufacturing are limited in the size of integrated circuit (IC) dies they can produce, restricting the area to no greater than 22 millimeters by 33 millimeters, which limits the complexity and number of circuits that can be integrated into a single die.
Innovation Solution
The development of large IC dies with subvolumes of different functionalities, exceeding conventional size limitations, by using multiple photomasks to pattern distinct layers and stitching subvolumes with electrical pathways, allowing for larger lateral dimensions and increased circuit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional photolithographic techniques are used for high-volume manufacturing, then manufacturing precision and ease of manufacture are maintained, but the area of IC dies is limited to no greater than 22 millimeters by 33 millimeters
Solution Approach 1:
The patent divides a large IC die into multiple subvolumes, each patterned separately using conventional photolithography with multiple photomasks. These subvolumes are then stitched together with electrical pathways to form the complete large-area die, enabling areas exceeding 750 square millimeters while maintaining manufacturing precision
Solution Approach 2:
The patent extends the manufacturing approach into the lateral dimension by stitching multiple patterned subvolumes together with electrical pathways, transitioning from a single photolithography field to a multi-subvolume assembly, thereby achieving die areas that exceed conventional single-die limitations
2Quantity of substance
If the area of IC die is increased beyond conventional limitations, then circuit density and computing power are enhanced, but manufacturing complexity increases due to multiple photomasks and stitching requirements
Solution Approach 1:
The large IC die is segmented into multiple functional subvolumes that can be patterned independently using multiple photomasks. Each subvolume contains specific circuits or components, and they are subsequently stitched together with electrical pathways, allowing high circuit density while managing manufacturing complexity through modular processing
Solution Approach 2:
The patent creates a universal manufacturing framework that can produce large-area IC dies with diverse functionalities by integrating multiple subvolumes, each capable of containing different circuit types (e.g., logic, memory, I/O), thereby achieving multi-functionality in a single large die
Data Source
Figure 1A~1C
Figure 2
Figure 3~4B
AI summary
Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.