Very Large Integer Adder Tree with Independent Carry Accumulation
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Solution Overview
Problem
Conventional adder circuits in integrated circuits, such as FPGAs, face challenges with large precision arithmetic operations due to significant area occupation, high power consumption, and latency issues, particularly in performing final addition operations for encryption and multiplication tasks involving operands of thousands of bits.
Innovation Solution
A restructured adder network is implemented, where inputs are segmented and processed independently, with each adder node handling carry bits separately from sum bits, allowing for a pipelined architecture that mimics infinite speed ripple carry adders, reducing area and latency by using decoders and prefix networks to generate and propagate signals concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If smaller adders are chained together to accommodate large precision arithmetic, then the adder circuit can handle thousands of bits of precision, but the final adder circuit occupies a substantial amount of area on the integrated circuit
Solution Approach 1:
The patent divides the final adder circuit into multiple independent sub-adder units, each handling a segment of the large precision arithmetic operation. These sub-adders operate in parallel rather than being chained sequentially, significantly reducing the area occupied by the overall adder circuit while maintaining the ability to handle thousands of bits of precision through coordinated parallel computation
2Measurement precision
If smaller adders are chained together to accommodate large precision arithmetic, then the adder circuit can handle thousands of bits of precision, but the final adder circuit consumes a relatively large amount of power
Solution Approach 1:
By segmenting the adder circuit into independent parallel sub-units, each sub-adder processes a portion of the computation simultaneously, reducing the total power consumption compared to a single large chained adder circuit that would require all components to operate sequentially at full power
3Measurement precision
If smaller adders are chained together to accommodate large precision arithmetic, then the adder circuit can handle thousands of bits of precision, but the final adder circuit introduces additional latency in the integrated circuit
Solution Approach 1:
The patent segments the addition operation into parallel sub-adder units that compute different segments of the result simultaneously, eliminating the sequential delay inherent in chained adder architectures and significantly reducing the latency for large precision arithmetic operations
Solution Approach 2:
The adder circuit performs preliminary parallel addition operations across multiple segments simultaneously, preparing intermediate results in advance rather than waiting for sequential carry propagation through chained adders, thereby reducing overall computation latency
Data Source
AI summary
An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.