Heterogeneous Die Stack Assembly via Laser-Debond Handler
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Solution Overview
Problem
Existing semiconductor manufacturing techniques face challenges in handling and assembling thin, delicate parts at large scales, particularly with finer pitch interconnections and heterogeneous components, which can lead to assembly failures and render entire packages or modules useless.
Innovation Solution
The implementation of an electronic package with a redistribution layer (RDL) and Through Silicon Via (TSV) dies, along with an epoxy layer and multi-stage testing, to support precise positioning, connection, and testing of heterogeneous parts at wafer and panel levels, ensuring reliable assembly and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional handling techniques are used for thin semiconductor parts, then the parts can be held and positioned during processing, but the parts are vulnerable to damage and assembly failures at large scales
Solution Approach 1:
The patent introduces a handler as an intermediary component that temporarily bonds to thin semiconductor parts ( dies, chips, chiplets) to provide mechanical support and enable precise positioning during manufacturing and assembly processes. The handler acts as a mediator between the fragile semiconductor parts and the manufacturing equipment, allowing handling at wafer and panel levels without directly manipulating the delicate parts themselves.
2Productivity
If heterogeneous parts with finer pitch connections are assembled at larger scales, then more components can be integrated, but assembly failures can render entire packages or modules worthless
Solution Approach 1:
The patent implements multi-stage testing approaches where semiconductor parts are tested at various points during the assembly process, not just at the beginning or end. Testing occurs after individual part preparation, after initial assembly steps, and before final packaging. This preliminary and intermediate testing allows defective parts to be identified and removed before they can compromise the entire heterogeneous assembly, enabling higher integration scales with maintained reliability.
3Manufacturing precision
If temporary handlers are bonded to parts for precise positioning, then accurate placement is achieved, but the bonding and debonding processes add complexity and potential damage risk
Solution Approach 1:
The patent utilizes parameter changes in the bonding and debonding processes, specifically employing laser-induced temperature changes to selectively debond the handler from the semiconductor parts. The handler is temporarily bonded using adhesives that can be selectively removed by laser heating, which changes the thermal parameters of the bonding interface. This allows precise positioning during assembly while enabling clean separation afterward without mechanical damage to the fragile semiconductor parts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise assembly and testing of heterogeneous parts, reducing the risk of assembly failures and ensuring the functionality of packages and modules by identifying and addressing faulty components before final assembly, thereby maintaining the integrity and value of expensive components.
Implementation Method 1
An epoxy layer is disposed on the RDL top surface and surrounds and attaches to all the TSV die sides and all the die sides
Data Source
AI summary
One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.