Laser-Assisted Defect Isolation for IC Testing

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Solution Overview

Problem

Conventional IC testers generate a large number of artifacts (false hot spots) during defect localization, increasing debugging time and negatively impacting product yield and profit margin.

Innovation Solution

A test system incorporating a scanning microscope module and a test module with a laser-assisted device alteration (LADA) analysis system, which uses a laser to perturb ICs, a comparator unit to match test vectors with prior failure signatures, and a software comparator to generate trigger pulses for identifying failed locations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional IC testers are used for defect localization, then testing can be performed, but a large number of artifacts (false hot spots) are generated increasing debugging time

Engineering Contradiction:
Improvedefect localization accuracyVSAvoiddebugging time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the defect localization process into two distinct phases: (1) initial conventional IC testing to identify potential failure locations, and (2) laser-assisted testing focused only on those specific locations. This segmentation allows the system to leverage the speed of conventional testing while eliminating the need to analyze artifacts from non-defect areas, thereby reducing debugging time without sacrificing localization accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary comparison mechanism that matches test vectors from conventional IC testing against a reference failure log containing known defect signatures. This intermediary step filters out artifacts by comparing against established patterns, allowing the system to distinguish true defects from false hot spots generated by conventional testing, thus reducing debugging time while maintaining accurate defect localization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional IC testers generate test artifacts, then comprehensive testing is achieved, but the large number of false hot spots increases debugging time and decreases product yield

Engineering Contradiction:
Improvetesting comprehensivenessVSAvoidproduct yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts only the relevant failure information from comprehensive conventional testing by comparing test vectors against a reference failure log. Instead of analyzing all test artifacts generated by comprehensive testing, the system extracts and focuses only on those artifacts that match known defect signatures, thereby maintaining testing comprehensiveness while eliminating false hot spots that would otherwise decrease productivity and product yield.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements a feedback mechanism where the reference failure log, built from previously identified true defects, is used to evaluate and filter results from conventional testing. This feedback loop allows the system to learn from past defects and progressively improve its ability to distinguish true defects from artifacts, maintaining comprehensive testing coverage while increasing productivity and product yield through reduced false positives.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If laser-assisted testing is applied to reduce false positives, then defect localization accuracy improves, but additional system complexity is introduced

Engineering Contradiction:
Improvedefect localization accuracyVSAvoidtest system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs dynamic testing where the laser perturbation parameters (wavelength, power, pulse duration) are adjusted based on the specific device under test and the type of defects being sought. This dynamic approach allows the system to optimize laser settings for different testing scenarios, improving defect localization accuracy while managing system complexity through adaptive rather than static configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent designs the laser-assisted testing system to be universal across different device types and defect modes. By using a configurable laser source that can operate at multiple wavelengths and power levels, the system achieves improved defect localization accuracy for various semiconductor devices without requiring entirely separate testing systems for each device type, thereby managing overall system complexity through multi-functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces false positives, streamlining defect localization and improving product yield by accurately identifying defect locations, thus enhancing the efficiency of the debugging process.

Implementation Method 1

perturb the DUT with a laser at a test (pixel) location

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS9958502B2Defect isolation methods and systems
Publication Date: 2018.05.01 GLOBALFOUNDRIES SINGAPORE PTE LTD
  • US9958502B2 patent drawing
  • US9958502B2 patent drawing
  • US9958502B2 patent drawing

AI summary

A test system for testing devices is disclosed. The test system includes a scanning microscope module and a test module. The scanning microscope module, when testing a device under test (DUT), is configured to perturb the DUT with a laser at a test (pixel) location. The test module includes a tester unit, a reference failure log containing prior failing compare vectors of interest, and a comparator unit which includes a software comparator. The tester unit is configured to perform a test run at the test location of the DUT with a test pattern. If the test run fails testing, the tester unit is configured to compare using the comparator unit to determine if failing test vectors of the test run matches a desired failure signature, and to generate a comparator trigger pulse if failing test vectors match the prior failure signature. The trigger pulse indicates that the test location of the DUT is a failed location.