Laser Attack Detection in IC Chips Using Parasitic Transistors
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Solution Overview
Problem
Existing laser attack detection devices for integrated circuit chips require additional structures, increasing complexity and bulk, and may not effectively detect attacks on the rear surface where interconnection metal tracks are located.
Innovation Solution
A device using an NPN bipolar transistor with an N-type buried layer and a parasitic PNP transistor, coupled with a comparator and resistor, detects current variations to identify laser attacks on the rear surface of the chip, allowing for early intervention without significant changes to the chip's structure or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing laser attack detection devices are implemented, then laser attack detection capability is provided, but chip structure complexity and bulk increase due to additional structures
Solution Approach 1:
The patent utilizes the inherent parasitic PNP transistor formed by the N-type buried layer and P-type epitaxial layer in standard CMOS technology. This self-service approach allows the detection function to be provided without adding external detection structures, as the parasitic transistor naturally forms part of the chip's existing architecture and can be activated to detect laser attacks.
Solution Approach 2:
The N-type buried layer serves multiple functions: it acts as a substrate for standard CMOS device fabrication and simultaneously forms the emitter region of a parasitic PNP transistor for laser attack detection. This multi-functionality eliminates the need for separate detection structures, reducing chip complexity while maintaining detection capability.
2Reliability
If detection devices are added to the chip, then laser attack detection is enabled, but the chip surface area increases
Solution Approach 1:
The patent merges the detection function with existing chip structures by utilizing the parasitic PNP transistor formed during standard CMOS fabrication. The detection circuit is integrated into the existing substrate and layer structure, allowing attack detection without occupying additional chip surface area.
3Reliability
If existing detection devices are implemented, then attack detection is provided, but power consumption increases
Solution Approach 1:
The parasitic PNP transistor is activated only when a laser attack occurs, causing localized heating that modifies the depletion layer. The detection mechanism relies on this attack-induced activation rather than continuous operation, significantly reducing power consumption compared to always-on detection circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables effective detection of laser attacks over a large area with minimal impact on chip surface area and power consumption, using existing components, and allows for immediate protection measures to be taken.
Implementation Method 1
detector of the variations of the current flowing between the base of said NPN bipolar transistor and the substrate
Implementation Method 2
bombarding chip areas with a laser beam while the chip is operating
Data Source
AI summary
A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate.