Laser-Modified Dielectric Etching for Flat IC Via Formation
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Solution Overview
Problem
Current IC die disintegration techniques face challenges such as high cost, lower insertion efficiency, and increased z-height due to limitations in monolithic integrated circuit fabrication, particularly in multi-chip architectures where integrating multiple IC dies into chip-scale units is complex, especially with the need to remove inter-die fill material for planarization and metallization.
Innovation Solution
The use of inorganic dielectric materials with selective laser exposure to modify and remove the material, allowing for reduced surface topography, formation of deep via holes, and complex features, enabling efficient packaging of IC dies in composite IC devices without solder-based joining materials, and facilitating thermal dissipation and stress reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip architectures are used to combine IC chips from heterogeneous silicon processes, then functionality and performance are improved, but integration complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the multi-chip integration process into distinct stages: depositing inorganic dielectric material over each chip, selectively modifying portions with laser exposure, and selectively removing modified portions. This segmentation allows complex heterogeneous integration to be managed through repeatable, modular processing steps rather than attempting to handle all complexity simultaneously.
Solution Approach 2:
The patent applies laser exposure to modify portions of the inorganic dielectric material before final removal. This preliminary modification creates a state that enables selective removal while preserving unmodified portions, allowing planarization and feature formation to occur in a controlled sequence that simplifies the overall integration process.
2Manufacturing precision
If inter-die fill material is removed to improve planarization, then surface flatness is improved, but manufacturing steps and time increase
Solution Approach 1:
The patent changes the physical-chemical parameters of the inorganic dielectric material through laser exposure, transforming it from a non-removable state to a selectively removable state. This parameter change enables rapid removal of excess material to achieve planarization without requiring multiple iterative polishing or etching steps, significantly reducing manufacturing time while maintaining surface flatness.
Solution Approach 2:
The patent replaces traditional mechanical planarization methods (such as CMP - chemical mechanical polishing) with a laser-based modification followed by selective removal process. This substitution eliminates the time-consuming mechanical polishing steps while achieving superior planarization precision through the selective modification and removal mechanism.
3Temperature
If inorganic dielectric material is used instead of organic materials, then thermal dissipation and stress reduction are improved, but material removal and processing difficulty increase
Solution Approach 1:
The patent introduces laser exposure as an intermediary process between depositing the inorganic dielectric material and removing excess material. The laser modification acts as a mediator that transforms the otherwise difficult-to-remove inorganic material into a selectively removable state, enabling easy removal of excess material while preserving the thermal dissipation benefits of the inorganic material in the final structure.
Solution Approach 2:
The patent applies laser exposure only to specific portions of the inorganic dielectric material that need to be removed, rather than treating the entire material uniformly. This local quality approach modifies only the necessary regions, making material removal easier where needed while preserving the intact inorganic material's thermal dissipation properties in regions where it is required.
4Adaptability or versatility
If deep via holes and complex features are formed, then device functionality is improved, but manufacturing precision requirements and process complexity increase
Solution Approach 1:
The patent performs laser modification of the inorganic dielectric material before removal, creating a preliminary prepared state that facilitates precise feature formation. This preliminary action defines the exact locations and shapes of via holes and complex features, enabling high manufacturing precision by controlling where material will be removed rather than attempting to directly etch complex geometries.
Solution Approach 2:
The patent replaces traditional mechanical or chemical etching processes with laser-based modification followed by selective removal. This substitution enables formation of deep via holes and complex features with superior precision because the laser can be precisely controlled to modify material at exact locations and depths, avoiding the precision limitations of conventional etching methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the packaging efficiency of IC dies by reducing surface topography, enabling precise feature formation, and improving thermal management, while avoiding the limitations of organic materials, thus addressing the challenges of cost, efficiency, and structural integrity in multi-chip integration.
Implementation Method 1
modifying a portion of the inorganic dielectric material with laser exposure
Data Source
AI summary
Composite integrated circuit (IC) device processing, including selective removal of inorganic dielectric material. Inorganic dielectric material may be deposited, modified with laser exposure, and selectively removed. Laser exposure parameters may be adjusted using surface topography measurements. Inorganic dielectric material removal may reduce surface topography. Vias and trenches of varying size, shape, and depth may be concurrently formed without an etch-stop layer. A composite IC device may include an IC die, a conductive via, and a conductive line adjacent a compositionally homogenous inorganic dielectric material.