Laser Driver Circuit Layout for Low-Parasitic LiDAR Pulsing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LIDAR systems face challenges due to parasitic inductances and capacitances, particularly in arrays of laser diodes, which lead to degraded electrical performance, limited current ratings, and poor current control in the nanosecond range.
Innovation Solution
A laser-driving device with an improved topology and chip layout is designed to reduce parasitic inductances and capacitances. This device includes a driver circuit with semiconductor switches and a control circuit that cyclically generates pulses to activate laser diodes, optimizing energy transfer and current routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional driver circuits with half-bridges and resonant tanks are used, then laser diodes can be activated selectively, but parasitic inductances and capacitances degrade electrical performance and limit current ratings
Solution Approach 1:
The driver circuit is divided into multiple independent push-pull stages, each capable of driving a separate laser diode. This segmentation allows optimized routing for each channel, reducing parasitic inductances and capacitances while maintaining selective activation capability.
Solution Approach 2:
The patent transitions from planar circuit layout to a three-dimensional stacked architecture where driver circuitry and laser diodes are vertically integrated. This dimensional change enables shorter current paths and reduced parasitic elements while improving current control in the nanosecond range.
2Measurement precision
If arrays of laser diodes are used to improve signal-to-noise ratio, then measurement accuracy improves, but parasitic inductances increase and degrade current control
Solution Approach 1:
Each laser diode in the array is driven by an independent push-pull stage, segmenting the control path for each element. This reduces the cumulative parasitic inductances that would otherwise degrade current control when multiple diodes are activated simultaneously.
Solution Approach 2:
The patent optimizes electrical parameters such as pulse width, amplitude, and timing for each laser diode channel independently. This allows precise control of current pulses in the nanosecond range, compensating for parasitic effects while maintaining improved signal-to-noise ratio through array operation.
3Power
If higher current ratings are achieved by increasing chip size, then current capability improves, but connection length to ground increases causing increased stray inductances and deteriorated switching time
Solution Approach 1:
The driver circuit and laser diodes are integrated in a vertical stacked configuration rather than planar layout. This three-dimensional arrangement enables high current ratings through multiple parallel channels while maintaining short ground connections, thus preserving fast switching times despite increased power capability.
Solution Approach 2:
The high current requirement is divided across multiple independent push-pull stages, each handling a portion of the total current. This segmentation allows each stage to maintain compact layout with short ground paths, achieving high overall current rating without increasing individual switching times.
Data Source
Figure 1
Figure 2~4
Figure 5
AI summary
In a driver circuit (100) couplable to laser diodes (LD_j), a semiconductor body (504) has a first surface (504a). A first control switch (S1) has a drain (DS1) coupled to a drain metallization (530) and a source (SS1) coupled to a first source metallization (532). The drain metallization is couplable to a power supply line (12). A second control switch (S1_0) has a drain (DS1_0) coupled to the drain metallization and a source (SS1_0) coupled to a second source metallization (533) . The first and second source metallizations are couplable to cathode terminals of the laser diodes (LD_j) and to a reference node (GND). A plurality of high-side switches (S2_j) have respective drains (DS2_j) coupled to the drain metallization (530) and respective sources (SS2_j) coupled to respective third source metallizations (534_j). Each third source metallization (534_j) is coupled to a respective drive output node (13_j) for driving an anode terminal (LDa_j) of a respective laser diode (LD_j). The drain metallization as well as the first, second and third source metallizations face the first surface (504a) of the semiconductor body (504), which is also configured to face the laser diodes (LD_j). The second source metallization (533) and the third source metallizations (534_j) are aligned with one another in a direction of alignment (540) and are superimposed, orthogonally to the direction of alignment (540), to the respective source terminals of the second control switch (S1_0) and of the high-side switches (S2_j).