Laser Fault Injection Detection Circuit for Security Chips

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Solution Overview

Problem

Existing chip security technologies are vulnerable to laser fault injection attacks, which can compromise data integrity and operational stability, particularly in security chips used in critical applications.

Innovation Solution

A detection circuit incorporating a first and second capacitor, switches controlled by clock signals, NMOS transistors, and a photosensitive element to detect laser fault injection attacks by monitoring voltage fluctuations, and trigger appropriate responses such as chip resets or data removal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a detection circuit is added to detect laser fault injection attacks, then chip security and robustness are improved, but device complexity increases

Engineering Contradiction:
Improvechip securityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The detection circuit merges multiple detection functions into a unified structure. The first and second detection units share common components including the photosensitive element, capacitors, and logic gates. This consolidation achieves comprehensive laser attack detection while minimizing the increase in overall circuit complexity through resource sharing and functional integration.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If multiple detection units are used to improve detection accuracy, then detection precision is improved, but device complexity increases

Engineering Contradiction:
Improvedetection accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The detection circuit is segmented into multiple specialized detection units, each capable of independent operation. The first detection unit monitors voltage changes through one pathway while the second detection unit monitors through another pathway. This segmentation enables parallel detection of different attack scenarios, improving overall detection accuracy and coverage without requiring a single overly complex detection mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multiple detection units are merged through shared components and coordinated logic. Both detection units share the photosensitive element, capacitors (first capacitor, second capacitor), and logic gate structures. This merging approach allows the system to achieve high detection precision through multiple monitoring pathways while controlling complexity through component sharing and integrated design.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The detection circuit effectively identifies laser fault injection attacks, enhancing the robustness and security of chips by preventing data loss and ensuring timely corrective actions.

Implementation Method 1

a photosensitive element, and a first NMOS transistor... The first voltage signal and the second voltage signal are configured to indicate the chip is attacked by laser fault injection

Methodology Applied
Scientific EffectPhotoelectric Effect: Photoelectric Effect

Data Source

PatentEP3979136B1Laser fault injection attack detection circuit for chip, and security chip
Publication Date: 2025.09.03 SHENZHEN GOODIX TECH CO LTD
  • EP3979136B1 patent drawingFigure 1
  • EP3979136B1 patent drawingFigure 2
  • EP3979136B1 patent drawingFigure 3

AI summary

Embodiments of the present disclosure provide a detection circuit for a laser fault injection attack on a chip and a security chip. The detection circuit includes a first capacitor, a second capacitor, a first switch, a second switch, a photosensitive element, a first NMOS transistor, and a second NMOS transistor. A drain of the first NMOS transistor is configured to output a first voltage signal, and a drain of the second NMOS transistor is configured to output a second voltage signal. The first voltage signal and the second voltage signal are configured to indicate that the chip is attacked by laser fault injection, thereby realizing detection of the laser fault injection attack, and ensuring the robustness and security of the chips.