Laser-Defined Silicon Grain Boundaries for Sub-10 nm Lines
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Solution Overview
Problem
Current methods for obtaining nanoscale lines in integrated circuits, such as multiple exposures or Extreme Ultra-violet (EUV) photolithography, are costly and complex, making it challenging to achieve high integration degrees with smaller line widths.
Innovation Solution
A method using a laser to form a nanoscale line by sequentially depositing a dielectric layer and an amorphous silicon layer on a substrate, irradiating a mask plate with the laser to crystallize silicon, and then removing the grain boundary to create a trench, which is used to obtain the nanoscale line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple exposures or EUV photolithography is used to obtain fine lines, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent changes the physical state of silicon from amorphous to crystalline through laser irradiation, creating grain boundaries that define line patterns. This parameter change (phase transition) enables nanoscale line formation without requiring complex photolithography processes, resolving the contradiction between manufacturing precision and process complexity
Solution Approach 2:
The patent replaces the optical-mechanical photolithography system with a laser-induced thermal field system. By using laser energy to melt and crystallize silicon, the process substitutes complex optical alignment and exposure mechanics with a more straightforward thermal processing approach, reducing device complexity while maintaining nanoscale precision
2Manufacturing precision
If multiple exposures or EUV photolithography is used to obtain fine lines, then manufacturing precision is improved, but cost increases
Solution Approach 1:
The patent uses a mask plate with holes that can be removed after forming grain boundaries, replacing the need for expensive reusable photolithography equipment. The mask plate serves as a disposable or consumable element that enables precise nanoscale line formation at lower cost, addressing the contradiction between manufacturing precision and manufacturing cost
Solution Approach 2:
By changing silicon from amorphous to crystalline state through controlled laser heating, the patent creates a self-organizing structure that defines line patterns. This physical parameter change eliminates the need for expensive EUV light sources and complex photolithography tooling, achieving cost-effective nanoscale manufacturing
3Ease of manufacture
If laser irradiation is used to crystallize silicon, then ease of manufacture is improved, but manufacturing precision may be affected by grain boundary control
Solution Approach 1:
The patent performs preliminary action by creating a mask plate with precisely spaced holes before laser irradiation. This pre-established geometric pattern controls the grain boundary formation during crystallization, ensuring manufacturing precision is maintained despite the simplified laser-based process
Solution Approach 2:
The mask plate acts as an intermediary between the laser energy and the silicon material. It translates the simple laser irradiation into controlled grain boundary patterns by allowing laser energy to pass through holes and initiate crystallization only in specific regions, thereby maintaining precision while keeping the overall process simple
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the cost-effective production of nanoscale lines with widths less than 10 nanometers, achieving high integration degrees suitable for advanced integrated circuit manufacturing without the need for expensive EUV photolithography.
Implementation Method 1
irradiating a mask plate by using the laser to perform a silicon crystallization in a partial region of the amorphous silicon layer
Implementation Method 2
perform a silicon crystallization in a partial region of the amorphous silicon layer
Implementation Method 3
removing the grain boundary by using a corrosion solution to form a grain boundary trench
Implementation Method 4
removing the silicon dioxide on the polycrystalline silicon by chemical mechanical polishing
Implementation Method 5
removing the polycrystalline silicon by using an alkaline silicon corrosion solution and retaining the silicon dioxide filled in the grain boundary trench
Data Source
AI summary
The present disclosure relates to a method of obtaining a nanoscale line by using a laser, including: forming a dielectric layer and an amorphous silicon layer on a substrate sequentially; irradiating a mask plate by using the laser to perform a silicon crystallization in a partial region of the amorphous silicon layer, where a grain boundary of a polycrystalline silicon formed by the silicon crystallization in the partial region of the amorphous silicon layer is determined by a spacing between holes with a regular shape on the mask plate; performing a planarization process on the grain boundary of the polycrystalline silicon of the amorphous silicon layer; removing the grain boundary by using a corrosion solution to form a grain boundary trench; and obtaining the nanoscale line on the substrate by using the grain boundary trench.