Laser-Modified Mold Cap Package for Stress Relief
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Solution Overview
Problem
Precision electronic devices face performance loss due to packaging stress caused by coefficient of thermal expansion (CTE) differences between organic packaging materials and silicon, leading to bending stresses that conventional methods like adding ceramic materials or silicon spacers cannot fully mitigate without increasing cost and complexity.
Innovation Solution
A package structure with recesses formed by laser ablation that extends inward from the package side, creating a spaced area between the semiconductor die and bond wire, reducing mechanical stress and enhancing circuit performance by thinning the package material over sensitive regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ceramic materials are used to overcome CTE differences, then stress effects on circuit performance are reduced, but device cost and manufacturing complexity increase
Solution Approach 1:
The patent applies local quality by creating a recess only in specific regions where stress relief is needed, rather than changing the entire package structure. The recess is positioned to provide stress relief while maintaining structural integrity elsewhere, allowing the use of cost-effective organic packaging materials without compromising circuit performance stability.
Solution Approach 2:
The patent changes the geometric parameter of the package structure by introducing a recess that modifies the stress distribution. This parameter change allows the organic packaging material to accommodate thermal expansion differences without requiring expensive ceramic materials, thus reducing cost while maintaining reliability.
2Reliability
If silicon spacers are added within the wire bond periphery, then stress effects are reduced, but device cost increases
Solution Approach 1:
The patent extracts the stress relief function from separate components (like silicon spacers) and integrates it directly into the package structure through a recess. This eliminates the need for additional silicon spacer components, reducing device cost while maintaining the stress mitigation effect.
Solution Approach 2:
The patent merges the stress relief function with the package structure itself by forming a recess in the molding compound. This combines multiple functions (packaging and stress relief) into a single integrated structure, eliminating the need for separate silicon spacers and reducing overall device cost.
3Stress or pressure
If lower modulus re-passivation layers are added to the top of the die, then point stresses are reduced, but overall bending stresses still develop
Solution Approach 1:
The patent addresses bending stress by introducing a dimensional change in the vertical direction through a recess in the package structure. This creates additional space that allows the die to accommodate thermal expansion without developing excessive bending stresses, complementing the point stress relief from re-passivation layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces mechanical stress on precision circuitry, improving device performance while maintaining cost-effectiveness and manufacturing simplicity by using existing laser ablation tools to create customized recesses in the package structure, thus minimizing strain and point stress effects.
Implementation Method 1
ablating a portion of the package structure to form a recess that extends inward from a package side toward a side of the semiconductor die
Data Source
AI summary
An electronic device includes a semiconductor die, a bond wire coupled to a side of the semiconductor die, and a package structure that encloses the semiconductor die and the bond wire. The package structure has a package side with a recess that extends inward from the package side toward the side of the semiconductor die. The recess has a bottom that is spaced apart from the side of the semiconductor die, and the bottom is spaced apart from the bond wire.