Laser-Plug Interposer With Tapered Interconnects for Signal Integrity
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Solution Overview
Problem
High-performance computing (HPC) semiconductor packages with column-shaped interconnect structures formed using the TSV process face challenges with signal integrity and increased parasitics due to their high aspect ratio and length, leading to increased overall height and space consumption in computing systems.
Innovation Solution
The use of tapered interconnect structures formed using a laser plug process reduces the thickness and length of the interposer, improving signal integrity and reducing parasitics by forming a multi-layer interposer structure with a passivation layer, redistribution layers, and tapered interconnects that pass through a silicon layer and buffer layer, which have a lesser aspect ratio compared to TSV process interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If column-shaped interconnect structures are formed using the TSV process, then electrical connectivity between IC dies, interposer, and substrate is achieved, but the high aspect ratio and length of the interconnect structures increase parasitics and degrade signal integrity
Solution Approach 1:
The patent applies curvature by transitioning from straight column-shaped interconnect structures to tapered interconnect structures with a gradual slope. This curved/tapered geometry reduces the effective electrical path length and parasitic effects while maintaining mechanical support and electrical connectivity functions, directly addressing the signal integrity issue caused by long straight interconnects.
Solution Approach 2:
The patent changes the geometric parameters of the interconnect structures by reducing their length and modifying their cross-sectional area distribution through the tapered profile. This parameter optimization reduces inductance and resistance, thereby improving signal integrity without compromising the electrical connectivity function.
2Reliability
If column-shaped interconnect structures with high aspect ratio are used, then vertical electrical connections are established, but the overall height of the semiconductor package increases consuming more space
Solution Approach 1:
The tapered curved profile allows the interconnect structures to achieve the necessary mechanical support and electrical connection with a reduced vertical footprint. The sloped geometry distributes the structural support function across a wider area, enabling shorter overall package height while maintaining connectivity.
3Strength
If the interposer thickness is increased to accommodate TSV process requirements, then mechanical robustness is achieved, but the overall package size and space consumption increase
Solution Approach 1:
The tapered curved interconnect structures provide mechanical support with reduced thickness by distributing structural loads more efficiently across the interposer. The gradual slope geometry enhances mechanical strength while minimizing the required interposer thickness, thereby reducing overall package size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of the semiconductor package by increasing signal integrity, reducing parasitics, and minimizing the overall thickness, thereby saving space in computing systems while reducing warpage and stress.
Implementation Method 1
formed using a laser plug process
Data Source
AI summary
Some implementations herein describe a semiconductor package. The semiconductor package, which may correspond to a high-performance computing semiconductor package, includes an interposer. The interposer includes tapered interconnect structures formed using a laser plug process. The tapered interconnect structures may include a length that is lesser relative to a length of the column-shaped interconnect structures formed using a through-silicon via process. Such a length reduces a thickness of the interposer and reduces a length of electrical connections through the interposer. In this way, a signal integrity may be increased and parasitics of the semiconductor package including the tapered interconnect structures may be reduced to increase a performance of the semiconductor package. Additionally, the reduced thickness of the interposer may reduce an overall thickness of the semiconductor package to save space consumed by the semiconductor package in a computing system.