Laser Via Formation in Stacked Chip Packages
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Solution Overview
Problem
In semiconductor devices with embedded chips, the formation of via holes using laser beams often damages the chip's electrode pads, leading to reliability issues and increased production costs.
Innovation Solution
A stacked chip package structure is developed, featuring first and second chips with stud and pillar bumps, encapsulated by a conductive material, where the via holes are formed by a laser process that exposes the stud bumps, preventing pad damage and enhancing bonding strength through roughened surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If via holes are formed by laser beam irradiation through the insulating layer, then via holes can be created to electrically connect electrode pads, but the electrode pads may be flown apart and damaged
Solution Approach 1:
The patent applies preliminary action by forming a protective layer over the electrode pads before laser via hole formation. This protective layer is specifically designed to withstand laser irradiation and prevent pad damage during the via hole creation process, thereby resolving the contradiction between ease of manufacture and reliability
2Productivity
If chips are embedded in substrates with insulating layers, then semiconductor devices can be manufactured, but the overall thickness increases and production cost increases
Solution Approach 1:
The patent employs thin film technology by using a thinly-controlled insulating layer and a compact protective layer structure. These thin films enable chip embedding and via hole formation while minimizing the overall thickness increase, thus resolving the contradiction between manufacturing capability and thickness control
3Reliability
If protective measures are added to prevent pad damage during laser processing, then reliability improves, but production cost increases
Solution Approach 1:
The protective layer serves multiple functions simultaneously: it protects electrode pads during laser processing, provides a planar surface for subsequent processing, and can be integrated with existing insulating layer structures. This multi-functionality reduces the need for additional separate protective measures, thereby improving reliability while controlling production cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and yield of the chip package, reduces production costs, and achieves a thinner overall thickness by preventing pad damage during via hole formation and enhancing bonding strength.
Implementation Method 1
A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps
Data Source
AI summary
A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.