Latch Amplification Circuit With Clocked Pulse Noise Rejection

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Solution Overview

Problem

Semiconductor apparatuses often malfunction due to noise being misinterpreted as signals, leading to incorrect signal processing and potential system failures.

Innovation Solution

Incorporating a pulse generation circuit and an amplification circuit that generate and manage pulse signals in response to a clock, enabling signal amplification during specific periods while maintaining output levels during inactive periods, thereby reducing noise interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the amplification circuit continuously amplifies input signals, then signal processing accuracy is improved, but noise interference increases causing malfunctions

Engineering Contradiction:
Improvesignal processing accuracyVSAvoidnoise interference
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The amplification circuit operates periodically based on clock signals, enabling amplification only during specific time windows when valid signals are expected. This periodic operation allows the circuit to distinguish between legitimate signals and continuous noise, amplifying only the former while ignoring the latter.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit uses preliminary timing signals and enable periods to prepare for signal amplification before the actual signal arrives. By establishing the amplification window in advance based on clock timing, the circuit is ready to amplify only when valid signals are expected, preventing noise amplification.

Inventive Principle:
Principle #10Preliminary action

2Duration of action of moving object

If the pulse signal enable period is extended, then more signal processing time is available, but the clock high period may be insufficient causing timing conflicts

Engineering Contradiction:
Improvesignal processing timeVSAvoidclock high period availability
Core Design Contradiction:
Duration of action of moving objectVSLoss of time

Solution Approach 1:

The pulse signal enable period is designed to be dynamically adjustable and is set shorter than the clock high period. This dynamic timing arrangement ensures that signal processing completes within the available clock high period, preventing timing conflicts while allowing sufficient processing time for valid signals.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10615781B2Semiconductor apparatus
Publication Date: 2020.04.07 SK HYNIX INC
  • US10615781B2 patent drawing
  • US10615781B2 patent drawing
  • US10615781B2 patent drawing

AI summary

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.