Latch-Based Power-On-Reset Circuit for NOR SR Latch Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power-on-reset (POR) circuits are inefficient due to large area requirements, variability, and susceptibility to device variations and PVT changes, making them costly and unreliable for resetting latches like NOR SR latches.
Innovation Solution
A robust POR circuit design that uses a NAND SR latch to reset a NOR SR latch, employing a feedback mechanism and multiple inverters to provide a delayed control signal, optimizing area usage and improving reliability across power-up conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the resistor and capacitor in the RC circuit is increased to generate a sufficient high pulse for latching, then the reset function reliability is improved, but the circuit area cost increases substantially
Solution Approach 1:
The patent changes the fundamental parameters of the POR circuit by replacing the passive RC time-constant approach with an active latch-based circuit using transistors and logic gates. This allows the generation of sufficient reset pulses without requiring large resistor and capacitor values, thereby achieving reliable latching with reduced circuit area.
Solution Approach 2:
The patent substitutes the mechanical/passive RC charging-d discharging mechanism with an active electronic latch circuit that uses transistor switching and logic gate feedback. This replacement enables precise control of the reset pulse timing and amplitude without being constrained by the physical size of passive components.
2Manufacturing precision
If multiple inverters are added to the delay circuit to provide substantial delay at slow supply ramp, then the reset timing accuracy is improved, but the circuit area and variability increase
Solution Approach 1:
The patent employs feedback mechanisms within the latch circuit where the output of the logic gates feeds back to control the switching of transistors. This feedback approach creates a self-regulating delay mechanism that achieves accurate reset timing without requiring a long chain of inverters, thereby reducing circuit area and minimizing variability.
Solution Approach 2:
The latch circuit is designed to anticipate the supply voltage ramp by using the rising edge detection capability of the transistors and gates. The circuit prepares the reset pulse generation in advance by monitoring the supply voltage through the latch feedback mechanism, achieving accurate timing without excessive delay stages.
3Ease of manufacture
If a conventional RC circuit with delay circuit is used, then the implementation is simple, but the circuit is susceptible to failure with device variations and PVT changes
Solution Approach 1:
The patent introduces dynamic behavior through the latch circuit where transistors and logic gates actively respond to supply voltage changes in real-time. This dynamic adaptation allows the circuit to maintain reliable reset function across PVT variations, as the latch automatically adjusts its operation based on the actual supply conditions rather than relying on fixed RC time constants.
Solution Approach 2:
The latch-based POR circuit serves multiple functions: it detects supply voltage rise, generates the reset pulse, and provides timing control, all within a single integrated structure. This multi-functionality makes the circuit more robust to device variations compared to the specialized RC-circuit-approach, while maintaining ease of manufacture through standard logic gate implementation.
Data Source
AI summary
Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.