Latch-Based Neural Network Weight Parity Detection
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Solution Overview
Problem
Deep learning neural networks face issues due to bit flips in stored neural network weights, which can significantly affect the order of magnitude and interfere with processing, particularly in non-volatile memory (NVM) arrays, where a single bit flip error can have substantial impacts depending on its location within floating-point numbers.
Innovation Solution
Implementing a device with a non-volatile memory array and processing circuitry on a die that includes latches for reading neural network weights and performing a linear sequence of operations to set the weight to zero if a parity error is detected, while leaving the weight unchanged if no error is found, utilizing on-chip latches for high-speed in-memory processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction coding is used to address bit flip errors in neural network weights, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the error detection and correction functionality from traditional ECC coding schemes and implements it using the existing latch infrastructure already present in the NVM die. By taking out the essential error handling function and realizing it through simple latch operations rather than complex coding, the solution improves reliability without proportionally increasing device complexity.
Solution Approach 2:
The NVM die performs error detection and correction autonomously using its built-in latch circuitry. The system self-services by detecting parity errors and automatically trimming affected weights without requiring external intervention or complex ECC mechanisms, thereby maintaining simplicity while improving reliability.
2Reliability
If traditional error correction methods are applied to neural network weights in NVM, then bit flip errors are addressed, but processing speed decreases due to complex operations
Solution Approach 1:
The patent replaces complex mechanical/ECC-based error correction systems with a simpler latch-based operational sequence. By substituting traditional ECC algorithms with direct latch manipulation (XOR operations, shifts, and conditional zeroing), the system achieves error correction at high speed without the computational overhead of conventional methods.
Solution Approach 2:
The solution changes the operational parameters from complex multi-step ECC algorithms to a simplified linear sequence of latch operations. This parameter change in the correction methodology enables fast processing by reducing the number of operations required while maintaining effective error correction capability.
3Reliability
If parity error detection and trimming operations are performed using traditional processing methods, then erroneous weights are corrected, but the operations become non-linear and slower
Solution Approach 1:
The patent introduces dynamic adaptability to the error correction process by using conditional latch operations that respond to parity check results. The linear sequence of operations dynamically adjusts its behavior based on detected errors, enabling efficient processing by avoiding unnecessary operations when no errors are present while maintaining robust correction when errors occur.
Solution Approach 2:
The system performs preliminary parity checking operations to identify erroneous weights before applying the trimming operation. This preliminary action enables the system to efficiently determine whether correction is needed, avoiding unnecessary processing and improving overall productivity by implementing a linear, condition-based operation sequence.
Data Source
AI summary
Latch-based methods and apparatus for performing neural network weight parity detection on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network weight data are described, particularly for use with floating point number values. Upon detection of a parity error in a neural network weight, the erroneous weight is set to zero to trim the corresponding neuron from the network, thus preventing the erroneous value from significantly affecting the network, particularly in situations where the bit flip would otherwise affect the magnitude of a floating-point weight value. The exemplary latch-based procedures described herein are linear procedures that do not require logic decisions. Procedures are also described that assess an amount of degradation in the NVM array based on parity bit data collected in the latches. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.