Latch-Chain Power Supply Voltage Detection for IC Voltage Sag
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Solution Overview
Problem
Integrated circuits face voltage sag issues due to rapid load changes, leading to potential circuit failure, necessitating real-time power supply voltage detection and regulation to maintain stable voltage levels.
Innovation Solution
A power supply voltage detection apparatus comprising a buffer string and latch chains connected to an integrated circuit power supply network, where the voltage regulation module detects voltage changes by analyzing data output from latches, allowing for precise voltage monitoring and regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If real-time voltage detection is implemented using traditional methods, then voltage monitoring capability is improved, but detection accuracy is insufficient to detect small voltage changes
Solution Approach 1:
The detection circuit is segmented into multiple latch chains (first latch chain, second latch chain, etc.), each responsible for detecting voltage changes within specific time intervals. This segmentation allows the system to achieve high detection accuracy by comparing outputs from multiple chains while keeping each individual chain relatively simple in structure.
Solution Approach 2:
The patent introduces a delay circuit as an intermediary element that delays the clock signal to generate different time intervals for different latch chains. This intermediary mechanism enables precise control of detection timing without requiring complex timing control logic, thus maintaining device simplicity while achieving high measurement precision.
2Area of stationary object
If detection circuit area is minimized, then integration efficiency is improved, but detection accuracy may be compromised
Solution Approach 1:
Multiple latch chains share common components including the delay circuit, clock signal source, and voltage input node. This merging of resources allows the detection system to achieve high accuracy through multiple measurement chains while minimizing the total circuit area by eliminating redundant components.
Solution Approach 2:
The delay circuit serves multiple functions: it generates time intervals for different latch chains, controls the timing of voltage sampling, and enables the system to detect voltage changes across different time periods. This multi-functionality reduces the need for separate timing control circuits for each latch chain, thereby reducing overall area while maintaining detection accuracy.
3Adaptability or versatility
If the detection system is adapted to various frequencies, then versatility is improved, but time delay regulation complexity increases
Solution Approach 1:
The delay circuit is designed with dynamic characteristics that allow it to automatically adapt to different clock frequencies. The delay amount is proportional to the clock period, so when the clock frequency changes, the delay circuit naturally adjusts its delay time accordingly. This dynamic behavior enables the system to maintain proper timing relationships across different frequencies without requiring manual or automated recalibration.
Solution Approach 2:
The system achieves frequency adaptability by allowing the delay parameter to change proportionally with the clock frequency. When the clock frequency increases, the delay time automatically decreases, and vice versa. This parameter change approach maintains the correctness of voltage change detection across different operating frequencies without introducing additional complexity for frequency compensation or calibration.
Data Source
AI summary
The application provides an apparatus, a system, a detector and a detection method for power supply voltage detection. The apparatus connected to an integrated circuit power supply network comprises: a power supply voltage detector, comprising: N buffers, wherein an input terminal of a first buffer is connected to a clock signal, and output terminals of other buffers are connected to the input terminal of an adjacent buffer; N latch chains, each of which comprises M latches, wherein a clock input terminal of each latch is connected to a clock signal, a D terminal of a first latch of each latch chain is connected to the output terminal of a corresponding buffer, and Q terminals of other latches are connected to the D terminal of an adjacent latch, wherein M and N are positive integers, the VDD terminal of each latch is connected to an area in an integrated circuit power supply network where a power supply voltage is to be detected, and a grounding terminal of each latch is connected to a ground; and a voltage regulation module connected to the Q terminal of each latch and configured to detect data output of each latch to determine a magnitude of a power supply voltage.