Latch Circuit Timing Control for DAC Noise Reduction
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Solution Overview
Problem
Conventional digital analog converters (DACs) in display apparatuses generate noise, particularly at center grayscale, due to insufficient stabilization time as the number of pixels increases, affecting image quality.
Innovation Solution
A latch circuit is introduced to control the timing of the most significant bit (MSB) signal, allowing for controlled enable and disable levels, which is used in conjunction with a digital analog converter (DAC) to reduce noise by managing the switching operations of the first and second switching units across different operation voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased to achieve higher resolution, then the input image reproduction precision is improved, but the stabilization time becomes insufficient and DAC noise affects the image
Solution Approach 1:
The latch circuit performs preliminary action by controlling the timing at which the MSB signal level becomes an enable level before the DAC conversion process. This advance timing control ensures that the switching units have sufficient stabilization time before the actual data transition occurs, preventing noise generation while maintaining high pixel count for UHD resolution.
2Ease of manufacture
If CMOS switches are used in all operation voltage range to reduce component cost, then the component cost is reduced, but noise is generated at center grayscale
Solution Approach 1:
The latch circuit performs preliminary action by controlling the timing at which the MSB signal level becomes an enable level before the DAC conversion process. This advance timing control ensures that the switching units have sufficient stabilization time before the actual data transition occurs, preventing noise generation while maintaining high pixel count for UHD resolution.
Solution Approach 2:
The invention changes the timing parameter of the MSB signal level transition. By controlling when the MSB signal becomes enabled based on center grayscale conditions, the switching units can stabilize properly during voltage range transitions, eliminating noise at center grayscale while keeping the cost-effective CMOS switch architecture.
3Measurement precision
If the number of pixels is increased to achieve higher resolution, then the input image reproduction precision is improved, but DAC noise affects the image due to insufficient blank time
Solution Approach 1:
The latch circuit performs preliminary action by controlling the timing at which the MSB signal level becomes an enable level before the DAC conversion process. This advance timing control ensures that the switching units have sufficient stabilization time before the actual data transition occurs, preventing noise generation while maintaining high pixel count for UHD resolution.
Data Source
AI summary
An embodiment provides a latch circuit which outputs, to a digital analog converter (DAC), a digital signal including grayscale data, the latch circuit including a first latch configured to store the digital signal and a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level, based on a center grayscale. The grayscale data includes first grayscale data and second grayscale data.