Latch Circuit Layout for Micro Display Noise Reduction
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Solution Overview
Problem
In matrix-type display apparatuses, the layout of data latch and line latch circuits results in long interconnects that are prone to noise interference, making it difficult to arrange latch elements within the small pixel pitch of micro display panels used in devices like electronic viewfinders and head-mounted displays.
Innovation Solution
The layout of data latch and line latch circuits is rearranged such that M×N 1-bit latch circuits are arranged with data latch unit circuits and line latch unit circuits close to each other, allowing for shorter interconnects and improved noise tolerance, with the option to arrange these circuits in the column or row direction to minimize width and optimize pixel pitch alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data latch circuit and line latch circuit are spaced away from each other according to related art layout, then each circuit can be independently designed and manufactured, but the interconnect becomes long and prone to noise interference
Solution Approach 1:
The patent merges the data latch circuit and line latch circuit into a single integrated structure where both circuits are formed within the same pixel region. This combination shortens the interconnect distance between the two circuits, reducing noise interference while maintaining independent functional design through separate circuit blocks within the integrated layout.
Solution Approach 2:
The patent utilizes multi-layer interconnect structures and three-dimensional layout arrangements to position the data latch circuit and line latch circuit in different spatial layers or regions within the pixel. This dimensional arrangement reduces the physical distance and noise coupling between circuits while preserving independent manufacturability through standard semiconductor fabrication processes.
2Length of moving object
If latch circuits are arranged to cover small pixel pitch in micro display panels, then interconnection can be established easily, but the area occupied by latch circuits increases when number of gradation bits increases
Solution Approach 1:
The patent segments the latch circuit into multiple functional blocks including data latch units, line latch units, and selection circuits distributed within the pixel region. This segmentation allows efficient utilization of space by placing only necessary circuit elements within each pixel, reducing total area while maintaining compatibility with small pixel pitches through modular architecture.
Solution Approach 2:
The patent designs universal latch circuit blocks that can handle multiple gradation bits through time-division multiplexing and shared circuit resources. The same physical circuit structure serves multiple functions for different bit positions and timing requirements, reducing the area occupied by latch circuits regardless of the number of gradation bits required.
3Reliability
If data latch unit circuit and line latch unit circuit are arranged close to each other, then interconnect length is reduced and noise tolerance increases, but layout complexity increases
Solution Approach 1:
The patent applies local quality optimization by arranging data latch unit circuits and line latch unit circuits in close proximity specifically within each pixel region, while maintaining standardized interface structures and regular patterning. This localized close arrangement improves noise tolerance for critical data paths, while the overall layout maintains manufacturability through consistent design rules and modular repetition across the display panel.
Data Source
AI summary
A latch circuit for outputting data for M pixels present in one line on a display panel in a time-division manner for each pixel, in order to drive each pixel from among the M pixels based on N-bit data, includes M×N 1-bit latch circuits in which N 1-bit latch circuits are arranged in the column direction Y and M 1-bit latch circuits are arranged in the row direction X, each circuit latching 1-bit data. Each 1-bit latch circuit includes a data latch unit circuit that latches data corresponding to any one bit of the N bits at different timings for each row, a line latch unit circuit that simultaneously latches data from the data latch unit circuit in each row, and an output enable element that outputs data from the line latch unit circuit based on an enable signal for selecting any one column.