Radiation-Hardened Latch Circuit for SET Glitch Containment

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Solution Overview

Problem

Single event transients (SET) cause voltage glitches and pulses in integrated circuits, leading to performance disruption and degradation, as existing radiation-hardened circuits are ineffective in stopping the propagation of these glitches.

Innovation Solution

A radiation-hardened latch circuit design comprising multiple stages of N-channel and P-channel cascode stages with differential inputs and outputs, which effectively stops the propagation of SET-induced glitches by utilizing specific operational modes such as NOOP and N/A modes, and is integrated into a signal distribution circuit and integrated circuit architecture to prevent further disruption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If radiation-hardened latch circuits with multiple cascode stages are used to stop glitch propagation, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveradiation hardnessVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The latch circuit is divided into multiple independent cascode stages (first N-channel cascode stage, second N-channel cascode stage, cross-coupled P-channel cascode stage), where each stage processes signals independently to stop glitch propagation while maintaining overall circuit functionality

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate latch stages between input and output that act as mediators to capture and hold transient glitches, preventing them from propagating further through the circuit while allowing legitimate signals to pass through

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If multiple latch stages are used to reduce SET propagation, then reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveglitch propagation resistanceVSAvoidcircuit fabrication precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Different cascode stages use different transistor types (N-channel vs P-channel) optimized for specific functions: N-channel stages for input signal processing and P-channel stages for output and cross-coupling, with each stage having locally optimized characteristics for its specific role in glitch suppression

Inventive Principle:

Principle #3Local quality

3Reliability

If cascode stages with differential inputs are used to mitigate SET effects, then reliability is improved, but ease of manufacture decreases

Engineering Contradiction:

Improveradiation hardnessVSAvoidcircuit implementation ease

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent combines multiple functions into unified cascode stages that simultaneously provide differential signal processing, glitch capture, and signal transmission capabilities in a single integrated circuit block, reducing the number of discrete components needed

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10469062B2Circuit and method for reducing the propagation of single event transient effects

Publication Date: 2019.11.05 FRONTGRADE COLORADO SPRINGS LLC

AI summary

Circuits and a corresponding method are used to eliminate or greatly reduce SET induced glitch propagation in a radiation hardened integrated circuit. A clock distribution circuit and an integrated circuit portioning can be radiation hardened using one or two latch circuits interspersed through the integrated circuit, each having two or four latch stages.