Latch Circuit SEU Detection With Glitch-Suppressed Reset
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Solution Overview
Problem
Integrated circuits face challenges in efficiently detecting and correcting single event upsets (SEUs) without duplicating memory elements, which is costly and inefficient in terms of chip area usage, especially in harsh radiation environments.
Innovation Solution
Incorporating additional circuitry to monitor the output of memory elements, such as latching circuits, to detect SEUs and generate a single shot pulse that resets the memory element, thereby correcting the faulty output without duplicating the memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duplications of the integrated circuit are used in parallel to provide multiple outputs, then reliability against single event upset is improved, but chip area increases significantly
Solution Approach 1:
The patent uses a simplified copy approach by duplicating only the critical latching circuit portion rather than the entire integrated circuit. This selective duplication provides SEU protection through majority logic voting while consuming minimal chip area, directly resolving the contradiction between reliability and area.
Solution Approach 2:
The patent segments the protection mechanism by dividing the circuit into critical latching elements that require protection and non-critical elements that do not. Only the essential latching circuit is duplicated in parallel for SEU detection and correction, while the rest of the circuit operates normally, achieving reliability improvement with minimal area overhead.
2Difficulty of detecting and measuring
If additional monitoring circuitry is added to detect SEU, then detection capability is improved, but device complexity increases
Solution Approach 1:
The monitoring circuitry is integrated within the latching circuit itself, allowing the circuit to self-detect SEU events. The latching elements automatically generate error signals when SEU occurs, eliminating the need for separate external monitoring circuits and thus improving detection capability without significantly increasing overall device complexity.
Solution Approach 2:
The patent merges the SEU detection function with the existing latching circuit structure. The same latching elements that store data also serve as the detection mechanism for SEU events, combining multiple functions into a single integrated structure and avoiding the addition of separate complex monitoring circuits.
Data Source
AI summary
This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.