Latch-Based Clock Delay Using Duty Cycle Control
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Solution Overview
Problem
Existing clock delay circuits are sensitive to variations in process, frequency, voltage, and temperature, affecting the accuracy of the clock delay across a desired operating range.
Innovation Solution
A clock delay circuit that uses a latch to provide a delayed version of the input clock signal, with the delay controlled by a duty cycle of a third clock signal, reducing sensitivity to process, frequency, voltage, and temperature variations, and incorporating a dual edge detector circuit and duty cycle adjust circuit to achieve precise delay adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional delay elements are used to introduce delay to the input clock signal, then the delay can be adjusted, but the delay accuracy deteriorates due to sensitivity to process, frequency, voltage, and temperature variations
Solution Approach 1:
The patent changes the control parameter from direct delay element tuning to duty cycle control of a clock signal. By varying the duty cycle parameter of the third clock signal, the delay is adjusted without using traditional delay elements that are sensitive to PVT variations. This resolves the contradiction by maintaining delay adjustability while improving delay accuracy through a more stable control mechanism.
Solution Approach 2:
The patent introduces a latch as an intermediary component between the input clock signal and the output. The latch, controlled by the duty cycle of the third clock signal, mediates the delay function. This intermediary approach eliminates the direct use of sensitive delay elements while preserving the ability to adjust delay through duty cycle control, thereby resolving the accuracy versus adaptability contradiction.
2Measurement precision
If duty cycle control is used to adjust the delay, then the sensitivity to process, frequency, voltage, and temperature variations is reduced, but the circuit complexity increases due to the need for duty cycle adjust circuitry
Solution Approach 1:
The third clock signal serves multiple functions: it provides the timing reference for the latch, controls the delay amount through its duty cycle, and enables adjustable delay without requiring separate control circuits for each delay element. This multi-functionality reduces overall circuit complexity while maintaining high delay accuracy, resolving the contradiction between precision and complexity.
3Adaptability or versatility
If the delay is made adjustable across a wide range, then the adaptability to different system requirements is improved, but the variability and accuracy of the delay deteriorates
Solution Approach 1:
The patent implements dynamic delay adjustment through variable duty cycle control of the third clock signal. The duty cycle can be dynamically changed to provide different delay amounts, and the latch responds accordingly. This dynamic approach maintains delay consistency within each setting while providing wide adjustability across different settings, resolving the contradiction between adaptability and reliability.
Data Source
AI summary
A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.