Latch Clock Gating With Blocking Logic to Prevent A-B-A Race
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Solution Overview
Problem
Latch-based digital device designs face challenges in preventing race conditions, which can lead to unpredictable behavior due to the potential for data to race through B-latches and arrive at destination storage elements too early, especially when clock gating correlation with source or destination storage elements is not possible.
Innovation Solution
Incorporating a blocking element in the logical path from the B-latch to the destination storage element, where the blocking element takes inputs from the B-latch output and the clock gating component, ensuring data transparency only when the clock gating is active, and correlating clock gating with either the source or destination storage elements when possible, or using a free-running clock for the B-latch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a latch-based design is used to enable high performance and utilize both halves of a clock cycle, then productivity is improved, but race conditions may occur leading to unpredictable behavior
Solution Approach 1:
A blocking element is introduced as an intermediary component in the logical path from the latch to the destination storage element. This blocking element receives inputs from both the latch output and the clock gating component, and only allows data to pass through when the clock gating is enabled, thereby preventing race conditions while maintaining high-performance latch-based operation
2Reliability
If a blocking element is added to prevent race conditions, then reliability is improved, but device complexity increases
Solution Approach 1:
The blocking element merges multiple functions into a single component: it acts as both a data transmission gate and a race condition prevention mechanism. By combining the blocking function with the existing clock gating control logic, the design prevents race conditions without requiring separate complex control circuits
3Reliability
If clock gating correlation is implemented with source or destination storage elements, then reliability is improved, but ease of manufacture worsens due to layout constraints
Solution Approach 1:
The clock gating control is segmented into independent components: the clock gating component that controls the latch and the blocking element that controls data flow to the destination. This segmentation allows each component to be independently optimized and placed in the layout, improving manufacturability while maintaining the reliability benefits of clock gating correlation
Data Source
AI summary
A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.