Latch Clock Gating to Hold Output During Disable Periods
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Solution Overview
Problem
In electronic devices, latches continue to consume power even when their corresponding functions or circuits are disabled, leading to unnecessary power consumption due to signal passing during disabling periods.
Innovation Solution
An enable signal is used to configure the clock generator to set the clock signal to a 'hold' state when the function or circuit is to be disabled, preventing unnecessary power consumption by keeping the latch output unchanged during disabling periods, and this is achieved through a latch clock generator and input latch configuration using standard logic elements like OR gates and NAND gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the latch continues to operate during disabling periods to maintain signal passing capability, then the latch maintains operational readiness, but unnecessary power consumption occurs
Solution Approach 1:
The latch circuit dynamically transitions between operational and disabled states based on the enable signal. When disabled, the clock signal is held at a fixed logic level that prevents state changes, effectively putting the latch in a low-power standby mode while maintaining its ability to resume operation when enabled.
Solution Approach 2:
The patent changes the operational parameters of the latch by controlling the clock signal logic level. By setting the clock signal to a specific logic level (e.g., logic high) during disabling periods, the latch parameters are adjusted to prevent signal passing and reduce power consumption, while still maintaining the capability to resume normal operation.
2Speed
If the latch passes signals continuously to maintain responsiveness, then the latch remains responsive to input changes, but coupling noise increases
Solution Approach 1:
The latch dynamically controls signal passing based on the enable signal state. During disabling periods, the latch transitions to a state where it does not pass signals, thereby eliminating coupling noise generation. The latch can quickly transition back to signal-passing mode when re-enabled, maintaining responsiveness when needed.
Solution Approach 2:
The patent converts the potential harm of continuous operation (noise generation) into a benefit by using the same operational mechanism to suppress noise during disabling periods. By holding the clock signal at a fixed logic level, the latch eliminates noise while maintaining the structural integrity and readiness of the circuit.
3Reliability
If the clock signal continues to switch during disabling periods to maintain clock functionality, then the clock signal remains active, but power consumption increases
Solution Approach 1:
The enable signal preliminarily determines the state of the clock signal before actual operation occurs. When the enable signal indicates a disabling period, the clock signal is pre-set to a fixed logic level that prevents switching, thereby eliminating power consumption during these periods while maintaining the ability to resume normal clock functionality when needed.
Solution Approach 2:
The patent changes the parameter of the clock signal from active switching to fixed logic level based on the enable signal. This parameter change reduces power consumption during disabling periods while maintaining the clock signal's ability to return to normal operation, effectively managing energy loss without compromising overall functionality.
Data Source
AI summary
A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.