Latch Clock Locking in Semiconductor Circuits for Power-Save Stability
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Solution Overview
Problem
In semiconductor apparatuses, the level of stored signals can change when a floated input signal or clock is inputted during power saving mode, leading to abnormal operations when switching from power saving to normal mode.
Innovation Solution
A semiconductor apparatus with a clock control circuit that generates periodically transitioning latch control clocks and locks them to specific levels during power saving mode, ensuring no change in the level of previously stored signals, thereby preventing abnormal operations when switching back to normal mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the semiconductor apparatus enters power saving mode to reduce power consumption, then power consumption is reduced, but the latch control clocks may float causing stored signal levels to change and leading to abnormal operations
Solution Approach 1:
The clock control circuit proactively generates control signals to lock the latch control clocks to specific levels before floating can occur during power saving mode transition. This preliminary action prevents the harmful floating effect by establishing a stable state in advance, ensuring signal levels remain unchanged even when the apparatus enters low-power mode.
2Reliability
If the latch control clocks are locked to specific levels during power saving mode to prevent signal level changes, then signal stability is maintained, but the clock control circuit complexity increases
Solution Approach 1:
The clock control circuit performs multiple functions: it generates latch control clocks during normal mode, generates lock control signals during power saving mode transition, and maintains locked states throughout power saving mode. By integrating these diverse functions into a single circuit block, the patent achieves signal stability without proportionally increasing overall system complexity.
Solution Approach 2:
The clock control circuit changes its operational parameters based on mode: during normal operation it produces periodically transitioning clocks, while during power saving mode it switches to generating lock control signals that maintain fixed clock levels. This parameter change allows the circuit to adapt its behavior to different operational requirements without requiring entirely separate circuits for each mode.
Data Source
AI summary
A semiconductor apparatus includes a clock control circuit that at least one of generates a plurality of latch control clocks, which are periodically transitioned, in response to a power saving mode signal and a clock, and individually locks each of the plurality of latch control clocks to one of multiple levels regardless of the clock. The semiconductor apparatus also includes a latch circuit that stores an input signal in response to the plurality of latch control clocks and outputs the stored signal as an output signal.