Latch Clock Compare Circuit for Setup Fail Detection
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Solution Overview
Problem
Debugging setup fails in chip production is costly and time-consuming due to the lack of effective methods for detecting and preventing setup failures between latches, especially when probe pads are not available.
Innovation Solution
A circuit design incorporating a mimic combinational logic module and a clock compare module to delay clock signals and detect potential setup fails by generating an error signal if the delayed clock signal arrives after the original clock signal, thereby preventing incorrect latching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If debugging setup fails is performed without detection circuits, then device complexity is reduced, but reliability of chip production decreases due to undetected setup fails
Solution Approach 1:
The patent applies preliminary action by introducing detection circuits that proactively identify setup fails before they propagate through the system. The first detection circuit detects setup fails at the first latch output, and the second detection circuit detects setup fails at the second latch output, enabling early intervention and preventing defective data from affecting subsequent operations.
Solution Approach 2:
The patent uses intermediary elements in the form of detection circuits that act as mediators between the latches and the rest of the system. These detection circuits monitor the timing relationships and generate error signals that can trigger reset operations, thereby mediating the conflict between data flow continuity and setup fail prevention.
2Reliability
If detection circuits are added to detect setup fails, then reliability of latching increases, but device complexity and debugging costs increase
Solution Approach 1:
The patent applies segmentation by dividing the detection function into separate, modular detection circuits for different latches. Each latch can have its own detection circuit that independently monitors setup timing, allowing the system to scale detection capability according to need without requiring a monolithic complex detection system.
Solution Approach 2:
The detection circuits provide self-service functionality by automatically monitoring their own latch inputs and generating error signals when setup fails are detected. The circuits serve themselves by autonomously identifying timing violations without requiring external debugging intervention, thereby improving reliability while maintaining manageable complexity.
3Ease of manufacture
If probe pads are not available for debugging, then ease of manufacture is improved, but difficulty of detecting and measuring setup fails increases
Solution Approach 1:
The detection circuits serve as intermediaries that make setup fails detectable without requiring external probe pads. By incorporating built-in detection logic that monitors clock and data signal timing relationships, the system enables measurement and detection of setup fails through existing circuit outputs, eliminating the need for additional probe pad infrastructure.
Solution Approach 2:
The system provides self-detection capability through integrated detection circuits that automatically monitor for setup fails without requiring external debugging equipment. The circuits generate error signals internally that can be used to identify and correct setup timing issues, making the system self-sufficient for detection purposes.
Data Source
AI summary
A circuit for preventing a setup fail between a first latch and a second latch according to one embodiment of the present invention comprises a mimic combinational logic module and a clock compare module. The mimic combinational logic module is configured to receive a first clock signal for the first latch and to generate a delayed first clock signal, which is a delayed version of the first clock signal. The clock compare module is configured to provide a delayed second clock signal, which is a delayed version of a second clock signal for the second latch, to the second latch after receiving the delayed first clock signal and the second clock signal.