Latch Comparator Timing Without Delay Circuits
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Solution Overview
Problem
Existing comparison circuits require an appropriate delay time between clock signals to prevent through-current increase, necessitating additional circuitry like half latch circuits, and they are not efficient in power consumption due to these timing requirements.
Innovation Solution
A comparison circuit design that uses a preliminary amplification circuit to generate control signals with specific change timing, allowing the latch circuit to compare and latch voltage differences without needing separate clock signals, thus eliminating the need for delay time settings and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If separate clock signals with delay time are used to operate the preliminary amplification circuit and latch circuit, then the circuits can be operated sequentially to prevent through-current, but the device complexity increases due to additional delay circuitry and half latch circuits
Solution Approach 1:
The patent merges the clock signal generation for the preliminary amplification circuit and latch circuit into a single unified clock signal system. The control signal generation circuit generates both clock signals CLK1 and CLK2 from a single input clock signal, eliminating the need for separate delay circuits and reducing overall circuit complexity while maintaining proper sequential operation to prevent through-current
Solution Approach 2:
The single input clock signal serves multiple functions by being processed to generate both CLK1 for the preliminary amplification circuit and CLK2 for the latch circuit. This multi-functional approach replaces what would traditionally require multiple independent clock sources and associated delay circuitry, reducing device complexity
2Reliability
If separate clock signals with delay time are used to operate the preliminary amplification circuit and latch circuit, then the circuits can be operated sequentially, but the device complexity increases due to additional delay circuitry
Solution Approach 1:
The control signal generation circuit acts as an intermediary that receives a single clock signal and generates the two required clock signals CLK1 and CLK2 with appropriate timing relationships. This intermediary circuit ensures reliable timing control for sequential operation of the preliminary amplification and latch circuits without requiring complex external delay circuitry
3Device complexity
If a single clock signal is used to operate both preliminary amplification circuit and latch circuit, then the device complexity is reduced, but through-current increases due to simultaneous operation
Solution Approach 1:
The patent segments the operation timing by generating two distinct clock signals CLK1 and CLK2 from a single input clock signal. CLK1 controls the preliminary amplification circuit while CLK2 controls the latch circuit, ensuring they operate in sequential non-overlapping phases. This segmentation prevents simultaneous operation that would cause through-current while maintaining a simple single-clock-input architecture
4Loss of time
If delay circuit is added to set appropriate delay time between clock signals, then the timing between preliminary amplification circuit and latch circuit is controlled, but the device complexity increases
Solution Approach 1:
The patent combines the delay function into the control signal generation circuit that processes the input clock signal to generate both CLK1 and CLK2. Rather than adding a separate delay circuit, the timing control is integrated into the clock signal generation process, reducing overall device complexity while maintaining appropriate timing between circuit operations
Data Source
AI summary
A comparison circuit includes a preliminary amplification circuit that amplifies a voltage difference between a first input voltage and a second input voltage and a latch circuit that compares magnitudes of the first input voltage and the second input voltage according to the amplified voltage difference and latch a comparison result. The preliminary amplification circuit converts the first input voltage and the second input voltage input with the falling edge timing of a clock signal into a first control signal and a second control signal, respectively that return from the reversal state at respective speeds corresponding to the first input voltage and the second input voltage. The latch circuit compares the first input voltage and the second input voltage according to the first control signal and the second control signal.