Latch Control Part Reduces Power in Solid-State Imaging Devices
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Solution Overview
Problem
Existing solid-state imaging devices with A/D conversion circuits have high power consumption due to continuous operation of latch circuits, which is problematic for high-frequency applications like digital still cameras with a large number of pixels.
Innovation Solution
The proposed solid-state imaging device incorporates a latch control part with a first and second logic gate and a switch circuit that only operates during specific timing, reducing power consumption by limiting the operation period of the latch part from the control signal output timing to a predetermined latch timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If latch circuits continuously operate to maintain valid state, then the circuit can respond to signals, but power consumption increases significantly
Solution Approach 1:
The latch circuit operates periodically rather than continuously. The enable signal activates the latch only during specific time intervals when data needs to be latched, allowing the circuit to enter a low-power state during idle periods. This periodic operation maintains signal response capability when needed while significantly reducing average power consumption.
Solution Approach 2:
The latch circuit transitions dynamically between different operational states (enabled/disabled) based on the enable signal. This dynamic state change allows the circuit to adapt its power consumption level according to actual operational needs, rather than maintaining a fixed high-power state continuously.
2Use of energy by moving object
If latch circuits are disabled to reduce power consumption, then power usage decreases, but the circuit cannot latch signals during the disabled period
Solution Approach 1:
The enable signal is activated in advance before the latch operation is needed, preparing the latch circuit to be in the valid state and ready to capture signals. This preliminary activation ensures that when signals need to be latched, the circuit is already prepared and can respond immediately without delay.
Solution Approach 2:
The latch circuit uses feedback mechanisms to maintain its latched state once data is captured. The Q and Q̅ outputs provide feedback to the internal logic, allowing the latch to hold the latched value stable even after the enable signal is deactivated, ensuring reliable signal storage during disabled periods.
3Speed
If high-frequency clock signals are used in delay part, then A/D conversion speed increases, but power consumption of latch circuits increases
Solution Approach 1:
The latch circuit is enabled periodically synchronized with the high-frequency clock cycles, allowing it to operate at high speed when needed while remaining disabled during idle clock cycles. This reduces the average power consumption proportionally to the duty cycle of the enable signal, while maintaining high conversion speed during active periods.
Data Source
AI summary
In this solid-state imaging device, an output signal of any one of a plurality of delay units that output signals of logic states in accordance with a level of a pixel signal is input to an input terminal of a latch circuit that latches a logic state of the output signal. A NAND circuit and an INV circuit stop until a control signal output timing at which a control signal in accordance with the level of the pixel signal is output, and operate after the control signal output timing. A switch circuit outputs the output signal of the one of the plurality of delay units through a signal line from an output terminal until the control signal output timing, and switches a connection at a latch timing after a predetermined time elapses from the control signal output timing such that the NAND circuit and the INV circuit latch the logic state of the output signal of the one of the plurality of delay units.