Latch Controller Timing for AD Conversion Accuracy
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Solution Overview
Problem
Conventional time-to-digital converter (TDC) type Analog-to-Digital (AD) conversion circuits in imaging apparatuses face challenges in reducing current consumption and maintaining AD conversion accuracy due to transient bounce and power voltage interference during latch operations.
Innovation Solution
The proposed imaging apparatus incorporates a clock generation unit with delay circuits, a comparing unit, a latch unit, and a latch controller that enables the latch unit to be valid at specific timings for AD conversion of both reset and signal levels, allowing for controlled latching and reduced current consumption by optimizing latch operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the latch unit operates continuously to maintain AD conversion readiness, then the AD conversion accuracy is maintained, but the current consumption increases
Solution Approach 1:
The latch unit is configured to operate periodically rather than continuously. It is activated at specific timing (third timing) before the comparison end timing, performs latching at the fourth timing after comparison, and remains inactive otherwise. This periodic operation reduces current consumption while maintaining AD conversion accuracy by ensuring the latch is ready at critical moments.
Solution Approach 2:
The latch unit is activated at a third timing that is earlier than the comparison end timing (second timing). This preliminary activation ensures the latch is in the valid state before the comparison completes, allowing accurate latching of the clock signal logic state without requiring continuous operation.
2Productivity
If the latch unit operates at all comparison timings, then all pixel signals are processed, but transient bounce affects AD conversion accuracy
Solution Approach 1:
The latch controller selectively activates the latch unit based on the type of pixel signal being processed. For reset level signals, the latch is activated; for signal level AD conversions, the latch is not activated. This selective operation avoids transient bounce interference in signal level conversions while maintaining processing capability.
Solution Approach 2:
The latch unit's operational state is dynamically controlled based on the specific conversion requirements. The latch controller adjusts the latch validity timing according to whether a reset level or signal level conversion is being performed, optimizing both accuracy and productivity for different signal types.
3Measurement precision
If the latch unit is activated early to ensure readiness, then AD conversion accuracy is improved, but the operation period increases causing higher current consumption
Solution Approach 1:
The latch unit is activated at a third timing that is earlier than the comparison end timing, providing sufficient time for the latch to be ready. However, the activation is limited to only what is necessary - the latch is deactivated after the fourth timing following comparison completion. This balances early activation benefits with minimizing operation duration.
Data Source
AI summary
An imaging apparatus capable of reducing deterioration of AD conversion accuracy is provided, wherein, when performing the AD conversion on a pixel signal corresponding to a reset level, a latch control unit causes a latch circuit of a latch unit to enter an enabled state (third timing) at a first timing according to a comparison start in a comparing unit, and then causes the latch circuit of the latch unit to execute latching at a fourth timing at which a predetermined time has lapsed from a second timing according to a comparison end in the comparing unit. Further, when performing the AD conversion on the pixel signal corresponding to the signal level, the latch control unit causes the latch circuit of the latch unit to enter the enabled state at the second timing according to the comparison end in the comparing unit.