Latch Delay Circuit Layout for Clock Skew Compensation
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges with clock skew due to manufacture variations and interconnect delays, leading to insufficient data retention and setup times, which can result in erroneous data fetching in flip-flop circuits.
Innovation Solution
A semiconductor integrated circuit design that includes a latch circuit with a delay circuit having a first delay section formed by connecting logic devices in series and a second delay section with a delay time equal to the interconnect delay time, reducing clock skew without the need for a complex clock tree structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock tree structure with buffers is used to reduce clock skew, then clock skew is reduced, but device complexity and design difficulty increase
Solution Approach 1:
The patent extracts the delay compensation function from the complex clock tree structure and implements it locally at each latch circuit using simple delay circuits. Each latch circuit independently measures its own clock skew and compensates for it, eliminating the need for global clock tree optimization and complex buffer insertion calculations.
Solution Approach 2:
Each latch circuit autonomously measures its own clock skew and adjusts its delay time without requiring external intervention or complex global optimization. The latch circuit serves itself by independently compensating for its specific clock skew, simplifying the overall design process.
2Reliability
If buffers with great delay time are inserted into clock signal lines, then clock skew is reduced, but layout area increases
Solution Approach 1:
The patent applies delay compensation locally at each latch circuit rather than using large buffers in the clock signal path. Each latch circuit has its own small delay circuit tailored to its specific skew requirements, reducing the need for large buffer layouts while maintaining effective skew compensation.
3Reliability
If the number of logic devices in delay circuit is increased to match clock signal path, then clock skew is reduced, but device complexity increases
Solution Approach 1:
The patent implements delay compensation that matches the clock signal path delay exactly by using an equivalent number of logic devices. This partial action approach compensates only for the specific skew caused by the clock path without over-compensating, maintaining simplicity while achieving the required delay matching.
Data Source
AI summary
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.