Latch Output Feedback for Single Event Upset Correction
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Solution Overview
Problem
Existing integrated circuits face challenges in efficiently detecting and controlling single event upsets (SEUs) within memory elements like D-type flip flops, leading to logic errors that can propagate and require costly duplication to mitigate.
Innovation Solution
Incorporating additional circuitry to monitor the output of memory elements, generate a single shot pulse upon detecting an SEU, and use this pulse to reset the memory element, thereby suppressing glitches and maintaining the original voltage level without duplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duplications of the integrated circuit are used in parallel to provide multiple outputs simultaneously, then reliability is improved by providing multiple outputs that are not impacted by single event upset, but device complexity increases and chip area increases
Solution Approach 1:
The patent implements a feedback mechanism where the output of the latching circuit is monitored and fed back to detect single event upsets. When an upset is detected (voltage level transition), a clear signal is generated to reset the latching circuit, correcting the error without requiring duplication. This feedback-based error correction resolves the contradiction by maintaining reliability through active monitoring and correction rather than passive redundancy.
Solution Approach 2:
The latching circuit incorporates self-correction capability through the clear signal mechanism. When a single event upset occurs, the circuit automatically detects the voltage level transition and generates its own clear signal to reset itself, or receives an external clear signal to do so. This self-service approach eliminates the need for duplicate circuits while maintaining reliability, as the circuit can correct its own errors without external intervention or redundancy.
2Reliability
If duplications of the integrated circuit are used in parallel, then reliability is improved, but area of the integrated circuit increases
Solution Approach 1:
The feedback mechanism monitors the latching circuit output and generates clear signals to correct single event upsets, eliminating the need for duplicate circuits. This approach maintains reliability while using minimal chip area, as only the original latching circuit plus simple monitoring logic is required, rather than multiple full duplications.
Solution Approach 2:
Instead of creating full physical duplications of the latching circuit, the patent creates a logical copy or model of the expected output behavior. The monitoring circuit compares actual output against expected behavior and detects deviations caused by single event upsets. This logical copying approach maintains reliability without the area cost of physical duplication.
3Reliability
If monitoring circuit is added to detect single event upset, then reliability is improved through local suppression, but device complexity increases
Solution Approach 1:
The monitoring circuit uses feedback from the latching circuit output to detect single event upsets. When a voltage level transition is detected, the feedback mechanism generates a clear signal to reset the latching circuit. This feedback-based approach improves reliability with minimal additional complexity, as the monitoring logic reuses existing circuit elements and signals rather than requiring completely independent monitoring systems.
Solution Approach 2:
The clear signal mechanism serves multiple functions: it acts as a reset signal for normal operation, serves as an error correction signal when single event upsets occur, and can be used for synchronization purposes. This multi-functionality reduces the need for separate dedicated error correction circuits, thereby improving reliability while minimizing additional device complexity.
Data Source
AI summary
This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.