Latch Feedback Delay Circuit for Soft Error Tolerance
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Solution Overview
Problem
Soft errors caused by alpha particles and neutrons can unintentionally alter data values in storage circuits, leading to improper operation of processors and memory circuits, as existing technologies fail to maintain data integrity against such spurious changes.
Innovation Solution
An event-tolerant circuit design featuring a feedback loop with a logic gate and delay element, which reinforces a storage voltage level and suppresses glitches by passing a voltage level only when it is maintained for a delay time T, preventing alterations to the storage node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional storage circuits are used, then the circuit structure is simple, but the data integrity is compromised due to soft errors from alpha particles and neutrons
Solution Approach 1:
The patent implements a feedback loop that continuously monitors the storage node voltage and reinforces it when glitches are detected. The feedback mechanism compares the current state with the expected state and applies corrective action to maintain data integrity, directly resolving the contradiction by improving reliability through active monitoring and correction.
Solution Approach 2:
The patent introduces an intermediary logic gate between the storage node and the feedback path that acts as a filter. This intermediary element selectively passes or blocks signals based on their validity, preventing spurious changes from propagating back to the storage node while allowing legitimate state transitions, thus improving reliability without requiring complete circuit redesign.
2Reliability
If a feedback loop with delay element is added to suppress glitches, then data integrity is improved, but the circuit complexity increases
Solution Approach 1:
The patent employs a delay element that anticipates the arrival of glitch signals by introducing a predetermined time delay in the feedback path. This preliminary timing adjustment ensures that transient spikes are filtered out before they can affect the storage node, achieving reliable glitch suppression through temporal discrimination rather than complex filtering circuits.
Solution Approach 2:
The patent utilizes the time parameter as a discrimination criterion, changing the temporal characteristics of the feedback signal through the delay element. By adjusting the delay time parameter, the circuit selectively responds to signal duration, allowing valid state changes (which persist longer than the delay) to pass while blocking shorter-duration glitches, thus improving reliability with a single adjustable parameter.
3Speed
If the logic gate passes voltage levels quickly, then the circuit response speed is fast, but glitches can alter the storage voltage level
Solution Approach 1:
The patent applies preliminary anti-action by introducing a counteracting delay in the feedback path that opposes the rapid propagation of glitch signals. The delay element creates a temporal window where spurious changes are neutralized before they can reach the storage node, effectively canceling out the harmful fast response to invalid signals while preserving the ability to respond to legitimate state changes.
Solution Approach 2:
The patent makes the circuit's response dynamic by combining fast logic gate operation with a time-based filtering mechanism. The system adapts its effective response time based on the duration of the input signal: short-duration glitches are automatically filtered out due to the delay, while longer-duration valid transitions are allowed to pass, achieving both speed and reliability through dynamic temporal discrimination.
Data Source
AI summary
An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event tolerant circuit may introduce a delay in a feedback loop, thereby passing the glitch value to an element in the feedback loop at different times, thus preventing the propagation of the glitch through the event tolerant circuit.