Latch-Based FIFO Circuit Layout for Lower Area and Power
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Solution Overview
Problem
Existing semiconductor circuits face challenges in reducing circuit area and power consumption, particularly in First In First Out (FIFO) circuits used for data storage.
Innovation Solution
A semiconductor circuit design incorporating a plurality of latch circuits, a selector, and a control circuit that operates based on control signals to sequentially acquire, hold, and output data, reducing the need for flip-flop circuits and simplifying the control circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional FIFO circuits are used, then data storage function is achieved, but circuit area increases
Solution Approach 1:
The FIFO circuit is segmented into multiple independent latch circuits (first latch circuit, second latch circuit, etc.), each capable of storing data independently. This segmentation allows the circuit to maintain data storage functionality while using simpler, smaller latch-based structures instead of traditional larger FIFO blocks.
Solution Approach 2:
The invention changes the operational parameters of the latch circuits by controlling their enable signals with clock phases. By switching latch circuits between active and inactive states based on clock signals, the circuit achieves FIFO functionality with reduced area compared to traditional always-active FIFO structures.
2Use of energy by stationary object
If traditional FIFO circuits are used, then data storage function is achieved, but power consumption increases
Solution Approach 1:
The latch circuits are activated periodically based on clock signals rather than continuously. Each latch circuit operates only during its designated time window controlled by clock phases, reducing overall power consumption while maintaining continuous data storage capability through the coordinated operation of multiple latches.
Solution Approach 2:
The invention dynamically changes the operational state of latch circuits by controlling enable signals, switching them between active and inactive modes. This parameter control allows the circuit to maintain data storage reliability while significantly reducing power consumption compared to traditional FIFO circuits that operate continuously.
3Area of moving object
If latch circuits with control signals are used, then circuit area is reduced, but control circuit complexity increases
Solution Approach 1:
The control functions for multiple latch circuits are merged into a unified clock signal distribution system. By using clock phases to control enable signals of different latch circuits, the invention reduces control circuit complexity while maintaining the area benefits of using latch-based structures.
4Productivity
If sequential acquisition operation is implemented, then data processing efficiency is improved, but circuit area increases
Solution Approach 1:
The sequential acquisition function is achieved by segmenting the data storage into multiple latch circuits that operate in sequence. Each latch circuit processes data during its designated time window controlled by clock phases, enabling efficient sequential data acquisition without requiring a large single FIFO structure.
Solution Approach 2:
The invention uses parameter changes in the enable signals of latch circuits, controlled by clock phases, to achieve sequential data acquisition. By dynamically switching latch circuits between active and inactive states, the circuit maintains high data processing efficiency while using minimal circuit area compared to traditional FIFO implementations.
Data Source
AI summary
A semiconductor circuit according to an embodiment of the present disclosure includes an input terminal, a plurality of latch circuits configured to sequentially acquire data at the input terminal and each configured to perform an acquisition operation for acquiring the data at the input terminal or a holding operation for holding the acquired data, in accordance with a voltage level of a corresponding control signal out of a plurality of control signals, a selector configured to perform a selection output operation for sequentially selecting any one of pieces of the data held by the plurality of latch circuits and for outputting the selected data, and a control circuit configured to control the operations of the plurality of latch circuits and the selector.