Latch-Based FIFO Testing for Area-Efficient Fault Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing FIFO buffers constructed from latches in integrated circuit devices lack comprehensive testing capabilities, particularly for stuck-at-1 faults and individual testing of data paths, limiting their effectiveness in ensuring data integrity and device reliability.
Innovation Solution
A system that can be selectively switched between normal operational mode and transition testing mode, utilizing banks of latches in a FIFO buffer and glue logic to generate internal control signals for thorough testing, including ATPG and LBIST testing, at a lower frequency clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If latches are used instead of flip flops in FIFO buffers, then area consumption is reduced by 45% to 50%, but testing capability is limited and cannot individually test data paths or detect stuck-at-1 faults
Solution Approach 1:
The patent applies dynamics by making the latch enable signals controllable and switchable between different states during normal operation and testing modes. The test control logic dynamically adjusts the enable signals to individual latch banks, allowing them to be selectively activated or deactivated based on testing requirements, thereby enabling comprehensive fault detection while maintaining area efficiency.
Solution Approach 2:
The patent segments the FIFO buffer into multiple independently controllable latch banks. Each latch bank can be individually enabled or disabled through separate enable signals generated by the test control logic. This segmentation allows selective testing of specific data paths and individual detection of stuck-at-1 faults in particular latch banks without affecting the entire FIFO structure.
2Area of stationary object
If latches are used in FIFO buffers, then area is reduced, but the ability to test for stuck-at-1 faults on latch enable pins is lost
Solution Approach 1:
The patent implements preliminary anti-action by pre-configuring the test control logic to generate appropriate enable signals that can force latches into specific states before testing occurs. The test control logic proactively sets up test conditions by controlling enable signals to prevent or detect stuck-at-1 faults, rather than attempting to detect them after they have manifested during normal operation.
Solution Approach 2:
The patent employs feedback mechanisms where the test control logic monitors the outputs of latch banks and uses this information to adjust enable signals accordingly. By observing the behavior of each latch bank under controlled enable conditions, the system can detect stuck-at-1 faults through feedback from the actual latch outputs during testing phases.
3Area of stationary object
If latches are used in FIFO buffers, then area consumption decreases, but individual testing of data paths from write register to FIFO and from FIFO to read register becomes impossible
Solution Approach 1:
The patent applies dynamics by implementing a test control logic that can dynamically switch between different testing configurations. The enable signals to latch banks are made controllable and switchable, allowing the system to adapt its testing mode to individually test the write path, read path, or both simultaneously, thereby achieving comprehensive testing flexibility without increasing area consumption.
Solution Approach 2:
The patent achieves universality by designing a test control logic that can perform multiple testing functions through a single unified structure. The same control logic generates enable signals that can selectively activate different latch banks for different testing purposes, enabling the system to universally test various data paths and fault conditions without requiring separate dedicated testing circuits for each function.
Data Source
AI summary
A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.