Latch-Flip-Flop Hybrid Register with Clock Gating for Scan Testing
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Solution Overview
Problem
Integrated circuits face challenges in reducing digital logic area while maintaining effective fault testing capabilities, as replacing flip-flops with latches leads to timing-related issues and increased power consumption, and existing scan-based designs are not well-suited for latch-based register circuits.
Innovation Solution
An integrated circuit device comprising a combination of latches and flip-flops, with clock gating circuitry to control latch transparency and facilitate scan testing, allowing for reduced digital logic area while maintaining fault testing efficacy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If flip-flops are replaced with latches to reduce digital logic area, then area is reduced, but timing control and fault testing capability deteriorate due to latch transparency
Solution Approach 1:
The register is segmented into multiple latches (first latch, second latch, third latch) with distinct control mechanisms. Each latch can be independently controlled regarding its transparency state, allowing some latches to be tested while others remain operational, thus resolving the conflict between area reduction and testing capability
Solution Approach 2:
The latches employ dynamic control of transparency through clock signals and control logic. The first latch transitions between transparent and non-transparent states based on clock phases, while the second latch's transparency is dynamically controlled by control logic to enable testing. This dynamic behavior allows the system to switch between operational and testing modes, maintaining both area efficiency and fault testing capability
2Area of stationary object
If latches are used instead of flip-flops, then digital logic area is reduced, but timing control deteriorates due to level-triggered transparency
Solution Approach 1:
The clock gating circuitry generates clock signals with periodic timing characteristics. The first latch receives clock signals during specific phases (first and second phases) while the second latch receives clock signals during different phases (second and third phases). This periodic clocking mechanism provides precise timing control over when each latch transitions between states, compensating for the inherent transparency issue of level-triggered latches
Solution Approach 2:
The clock gating circuitry acts as an intermediary between the control logic and the latches. It receives control signals and generates appropriately timed clock signals that gate the data flow into the latches. This intermediary mechanism provides precise timing control, ensuring that latches only become transparent at intended moments, thus resolving the timing control deterioration issue
3Area of stationary object
If latches are used to reduce area, then digital logic area is reduced, but power consumption increases due to continuous transparency
Solution Approach 1:
The latches operate with periodic clocking rather than continuous transparency. The first latch is clocked during specific phases while the second latch is clocked during different phases. This periodic operation ensures that latches spend most time in non-transparent (latched) state, reducing unnecessary data propagation and associated power consumption while maintaining area efficiency
Solution Approach 2:
The system dynamically controls latch transparency through phase-based clocking. During normal operation, latches transition to non-transparent states to prevent unnecessary data propagation. During testing phases, transparency is dynamically enabled only when needed. This dynamic control reduces average power consumption compared to continuously transparent latches, while preserving the area benefits of latch-based design
Data Source
AI summary
An integrated circuit device includes an n-bit register comprising: a plurality of latches and at least one flip-flop, and clock gating circuitry, which includes a clock signal coupled to the latches and the flip-flop. Each latch comprises a latch gating terminal configured to receive a gating signal, wherein a respective latch is configured to receive the gating signal that either corresponds to the clock signal or is determined according to a logical operation including the clock signal such that a transparency for each respective latch is controlled in dependence upon a level of the gating signal. The integrated circuit device is configured to operate in a scan test mode, wherein during a scan shift operation, an input signal terminal of the flip-flop is configured to receive a test input signal and the flip-flop is configured to load the test input signal to an output signal terminal of the flip-flop.