Latch-Based Fuse Read Circuit for Low-Voltage MOSFET Sensing
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Solution Overview
Problem
Existing fuse reading circuits face challenges in accurately determining the state of fusible links in low-voltage logic circuitry with high-voltage stand-off capability, particularly in MOSFET devices, due to threshold voltage variations and process variations.
Innovation Solution
A latch circuit and pair of voltage dividers generate a reference voltage and a testable fuse voltage, allowing comparison and latching of the greater voltage, operating at a slightly higher voltage than the reference voltage, which is less than the minimum supply voltage, enabling reliable fuse state detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If MOSFETs are fabricated with high-voltage stand-off capability (3.6V process), then they can provide high-voltage capability, but their threshold voltage VTH becomes close to low-voltage minimum supply voltage (VDD_MIN ≈ 1V), making fuse reading unreliable
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitors to specific voltage levels (VDD or VDD/2) before the actual fuse reading operation. This pre-charging ensures that when the fuse state is being detected, the capacitors are already at the correct reference voltages, allowing reliable comparison even when VDD is as low as 1V and close to the MOSFET threshold voltage. The preliminary setup of voltage references eliminates the reliability issue caused by the narrow voltage margin.
2Ease of operation
If a typical resistor comparison method is used to sense fuse state, then the fuse can be read, but the circuit requires voltage levels higher than VDD_MIN to operate reliably
Solution Approach 1:
The patent changes the operating parameters of the fuse reading circuit by using capacitive voltage division and comparison instead of traditional resistive comparison. The capacitors are charged to specific voltage levels (VDD or VDD/2) and then compared through a latch circuit. This parameter change allows the circuit to operate reliably at VDD_MIN ≈ 1V, as the capacitive references provide stable voltage levels even at low supply voltages, eliminating the need for higher voltage operation.
3Quantity of substance
If fuse arrays are scaled to large memory sizes (e.g., 1024 bits), then storage capacity increases, but circuit area and complexity increase
Solution Approach 1:
The patent applies universality by designing a single, compact latch circuit that can serve multiple fuse elements. The same latch circuit can be used to read different fuse states by selectively connecting the capacitors to different fuse nodes. This multi-functional approach allows large fuse arrays (e.g., 1024 bits) to be implemented without proportionally increasing the reading circuit area, as the core comparison logic remains shared and reusable across all fuse elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides predictable operation with reduced susceptibility to process/voltage/temperature variations, supports large memory arrays, and does not require additional pins, while using low-voltage logic circuitry with high-voltage stand-off capability.
Implementation Method 1
a pair of voltage dividers generate a reference voltage VREF and a testable fuse voltage VFUSE
Data Source
AI summary
Circuits and methods for reading fusible links that allows use of low-voltage logic circuitry utilizing devices that may have a high-voltage stand-off capability. Embodiments provide predictable operation that is less susceptible to PVT variations, allow the use of arrays of fuses that may be scaled to relatively large memory sizes, uses little integrated circuit area, and do not require extra pins for operation. Embodiments utilize a latch circuit and voltage dividers to generate a reference voltage VREF and a fuse voltage VFUSE, and then compares and latches the greater of those voltages. The circuitry does not require any more supply voltage than is needed to turn ON input pass transistors to the latch at a slightly higher voltage (VTH) than VREF. Since VREF may be about 0.1V, that turn-ON voltage may be as low as about 0.1V+VTH, and thus would be less than a VDD_MIN of about 1V.