Latch Inverter Laser Detection Circuit for Compact Chip Security
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Solution Overview
Problem
Existing laser detecting circuits face challenges in achieving high sensitivity while maintaining a small size, which is crucial for enhancing chip security against physical attacks.
Innovation Solution
The proposed laser detecting circuit incorporates a latch circuit with a first and second inverter, where the second inverter includes a series connection of PMOS transistors and a series stack structure of NMOS transistors, along with dummy transistors to enhance sensitivity and compactness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the circuit size is reduced to meet miniaturization requirements, then the chip package size decreases, but the laser detection sensitivity deteriorates
Solution Approach 1:
The inverter circuit is segmented into multiple transistor stages (first inverter with first and second NMOS transistors, second inverter with third and fourth NMOS transistors) with dedicated laser-sensitive regions. This segmentation allows each transistor to contribute to both size efficiency and detection sensitivity, resolving the contradiction between compact size and high sensitivity.
Solution Approach 2:
Specific regions of the transistor structures are designed with enhanced laser sensitivity (gate regions and channel regions of NMOS transistors), while maintaining overall circuit compactness. The first and third NMOS transistors are specifically configured to be sensitive to laser light, creating local sensitivity zones within the compact circuit structure.
2Ease of manufacture
If the circuit structure is simplified to reduce manufacturing complexity, then the manufacturing process becomes easier, but the laser detection sensitivity decreases
Solution Approach 1:
The laser detection function is merged with the normal inverter circuit logic function. The same transistors (first, second, third, and fourth NMOS transistors) perform both logical inversion operations and laser detection, eliminating the need for separate detection components and simplifying manufacturing while maintaining high sensitivity.
Solution Approach 2:
The inverter circuit serves multiple functions: it performs logical inversion operations and simultaneously detects laser light through its transistor structures. The gate and channel regions of the NMOS transistors are designed to respond to laser light while maintaining their switching functionality, achieving multi-functionality without increasing manufacturing complexity.
Data Source
AI summary
A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.