Latch Layout for Low-Power Soft Error Hardening
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Solution Overview
Problem
Existing low power flip-flop devices face challenges in optimizing soft error rate (SER) performance without compromising power consumption, silicon area, speed, and performance, particularly in applications where radiation-induced errors are a concern.
Innovation Solution
The design incorporates a pair of cross-coupled inverters with channel-connected regions having a reduced Linear Energy Transfer (LET) cross-section, utilizing layout techniques such as shared diffusion areas, proximate substrate and well ties, folded layouts, and dummy gates to minimize SER, while maintaining low power consumption and silicon area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low power flip-flop device is used, then power consumption is reduced, but soft error rate performance deteriorates
Solution Approach 1:
The latch device is segmented into distinct functional regions: a first region containing the first inverter and first storage node, and a second region containing the second inverter and second storage node. This spatial segmentation allows independent optimization of each region's radiation hardness while maintaining low power consumption through the shared clock pass transistor.
Solution Approach 2:
The patent applies local quality by creating asymmetric diffusion regions with different properties for each storage node. The first diffusion region and second diffusion region are configured with different characteristics to provide differential radiation hardening, where each node has tailored protection based on its specific soft error vulnerability.
2Reliability
If SER-hardened flip-flop design is used, then soft error rate is reduced, but power consumption increases
Solution Approach 1:
The patent merges the clock control function into a single shared clock pass transistor that controls both the first and second storage nodes. This consolidation reduces the total number of transistors compared to traditional SER-hardened designs, thereby reducing dynamic power consumption while still providing adequate radiation protection through the segmented diffusion regions.
3Reliability
If channel-connected region with reduced LET cross-section is used, then soft error rate is reduced, but device complexity increases
Solution Approach 1:
The clock pass transistor serves multiple functions: it acts as the clock control element for both storage nodes, provides radiation hardening through its channel-connected diffusion region configuration, and reduces overall device complexity by eliminating the need for separate control transistors for each node.
Data Source
AI summary
A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.