Latch Level Shift Circuit With MOS Current Control for Smaller Layout
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Solution Overview
Problem
The existing latch type level shift circuits in nonvolatile memory devices, such as F-MONOS, face challenges with large area occupation due to the need for large pull-down transistors to prevent penetration current, which is exacerbated by the requirement for multiple circuits in decoders.
Innovation Solution
A level shift circuit design incorporating a latch circuit with first and second inverter circuits, a first input MOS transistor, a second input MOS transistor, and a current-voltage control MOS transistor, which uses dual voltage terminals to suppress penetration current and allow for smaller pull-down transistors, thereby reducing the overall area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a latch type level shift circuit employs a pull-down transistor to suppress penetration current, then penetration current is reduced, but the transistor occupies a large area
Solution Approach 1:
The pull-down function is segmented into two parts: a main pull-down transistor for general operation and a penetration current suppression transistor specifically for suppressing penetration current during latch inversion. This segmentation allows each transistor to be optimized for its specific function, enabling the main pull-down transistor to be smaller while maintaining overall performance.
Solution Approach 2:
A penetration current suppression transistor is introduced as an intermediary element between the power supply and the latch circuit. This intermediary transistor is controlled by a penetration current suppression signal to selectively suppress penetration current only when needed (during latch inversion), allowing the main pull-down transistor to be reduced in size.
2Adaptability or versatility
If multiple latch type level shift circuits are disposed for decoder operation, then decoding functionality is achieved, but the total area increases significantly
Solution Approach 1:
The level shift circuit is segmented into functional modules (latch circuit, inverter circuits, input MOS transistors, penetration current suppression transistors) that can be independently optimized and replicated. This modular segmentation enables efficient area utilization when multiple circuits are instantiated for decoder applications.
Solution Approach 2:
The circuit parameters (transistor sizes, voltage levels) are optimized to achieve the minimum required area while maintaining decoder functionality. By carefully selecting transistor dimensions and operating parameters, the circuit achieves adequate performance with reduced area, allowing multiple instances to be packed more efficiently.
Data Source
Figure 1~2
Figure 3~4
Figure 5(A)~5(B)
AI summary
A level shift circuit includes: a latch circuit (Q5, Q6, Q7, Q8) including first (Q5, Q7) and second (Q6, Q8) inverter circuits; a first input MOS transistor (Q1) operating in accordance with an input signal; a second input MOS transistor (Q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control MOS transistor (Q9). The latch circuit (Q5, Q6, Q7, Q8) outputs a voltage having been converted from the input voltage in level. Each of the first and second input MOS transistors (Q1, Q2) receives the input signal at its gate terminal, and drives the latch circuit (Q5, Q6, Q7, Q8) in accordance with the input signal. The current-voltage control MOS transistor (Q9) is provided between the input MOS transistor (Q1, Q2) and the latch circuit (Q5, Q6, Q7, Q8), and is driven in accordance with an inversion operation of the latch circuit by receiving an input of the control voltage at its gate terminal.