Latch-Based Level Shifter Without Cascode HV Stages
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Solution Overview
Problem
Existing level shifters require a cascode structure to handle high voltages, leading to increased silicon area consumption and manufacturing effort due to the need for larger HV transistors, which is costly and inefficient.
Innovation Solution
A level shifter design that uses a latch with a reduced number of HV devices, avoiding the need for a cascode structure by employing a configuration where low and high supply voltages are shifted in parallel, with transistors biased by a medium voltage to prevent excessive voltage across HV transistors, thereby reducing the silicon area required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cascode structure is used to handle high voltages, then the ability to handle high output voltages is improved, but the silicon area consumption increases significantly
Solution Approach 1:
The patent extracts the essential function of voltage handling from the complex cascode structure and implements it using a simplified latch-based circuit. By removing the cascode configuration and using only necessary HV devices (T1-T4) in a latch structure, the design achieves high voltage capability with minimal silicon area, directly resolving the contradiction between voltage handling ability and area consumption.
Solution Approach 2:
The patent uses standard HV transistors without requiring specialized high-voltage cascode devices. By employing conventional HV transistors in a latch configuration rather than dedicated cascode structures, the design reduces manufacturing complexity and silicon area while maintaining the ability to handle high voltages up to 17V.
2Reliability
If the number of HV transistors is increased to handle higher voltages, then the high voltage capability is improved, but the manufacturing effort and cost increase
Solution Approach 1:
The patent extracts only the essential HV devices needed for voltage handling and eliminates unnecessary components. The latch structure uses minimal HV transistors (T1-T4) compared to traditional cascode designs, reducing manufacturing complexity and cost while maintaining high voltage capability through clever circuit configuration rather than component quantity.
Solution Approach 2:
The patent merges multiple functions into a single latch structure that simultaneously achieves voltage shifting, signal level conversion, and high voltage handling. By combining these functions in one compact circuit rather than using separate cascode stages, the design reduces the number of HV devices required and simplifies the manufacturing process.
3Reliability
If the transistor width is increased to handle higher voltages, then the voltage handling capability is improved, but the silicon area consumption increases
Solution Approach 1:
The patent applies different voltage handling requirements to different parts of the circuit. The latch structure uses HV transistors (T1-T4) only where high voltage stress occurs, while other parts of the circuit can use standard transistors. This localized approach to voltage handling minimizes the total silicon area required compared to increasing transistor width throughout the entire circuit.
Data Source
AI summary
In various embodiments, a level shifter and a method for operating the same are provided. The level shifter may include a low supply voltage terminal, a high supply voltage terminal, at least one input terminal, at least one output terminal, and a latch. The latch may configured to: store a predetermined logic state by setting a storage node to a voltage level in response to receiving a predetermined voltage level at the at least one input terminal; amend the voltage level at the storage node in response to receiving an amended voltage/s at the low supply voltage terminal and/or at the high supply voltage terminal; and output the predetermined logic state having the amended voltage level from the storage node to the at least one output.