Latch-Based Level Shifter Without Phase-Matching Logic
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Solution Overview
Problem
Existing level shifter architectures require additional circuitry and phase logic to generate phase-matched inverted and non-inverted signals, leading to increased power consumption and circuit size, as well as issues with phase delay and matching of differential outputs.
Innovation Solution
The use of latches that latch transitions in the input signal and apply a clear signal to prevent output buffer devices from being conductive at the same time, eliminating the need for phase logic and reducing circuit size by using differential outputs to generate both versions of the level shifted signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If phase logic is used to control output buffer devices to prevent simultaneous conduction, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent extracts and removes the phase logic circuitry from the level shifter design. Instead of using complex phase logic to control the timing of output buffer devices, the invention uses a simpler latch-based mechanism that inherently prevents simultaneous conduction of complementary buffers without requiring additional phase control logic, thereby reducing device complexity while maintaining power efficiency
Solution Approach 2:
The latch circuit automatically manages the state of output buffer devices based on the level-shifted signal itself. When the level-shifted signal transitions, the latch automatically updates its state, which in turn automatically controls the output buffer devices to be non-conductive during transitions, eliminating the need for external phase logic control
2Adaptability or versatility
If additional level shifters and buffer devices are used to generate phase-matched inverted signals, then signal completeness is improved, but device complexity increases
Solution Approach 1:
The patent makes the core level shifter circuit universal by designing it to inherently provide both phase-matched inverted and non-inverted outputs through its latch structure. The same latch circuit that performs level shifting also generates both signal versions simultaneously, eliminating the need for separate dedicated circuits for inverted signal generation and reducing overall device complexity
Solution Approach 2:
The patent merges the functions of level shifting and inverted signal generation into a single integrated circuit block. By combining the latch-based level shifter with inverted output capability in one unit, the design eliminates the need for separate level shifter circuits and phase logic that would otherwise be required to generate phase-matched inverted signals, thereby reducing circuit size
3Device complexity
If simple inverter is used to generate inverted signal, then circuit size is reduced, but phase matching is degraded
Solution Approach 1:
The patent performs the inversion action preliminarily within the latch structure itself during the level shifting process, rather than applying a simple inverter afterward. The latch circuit inherently generates the inverted state as part of its normal operation, ensuring that the inverted output is phase-matched with the non-inverted output from the moment of signal transition, avoiding the phase delay issues that would result from post-processing inversion
Data Source
AI summary
Embodiments of the present invention provide a device for level shifting an input signal. The device includes an output buffer that has: an output node, a p-FET coupled to a high reference voltage, and an n-FET coupled to a low reference voltage. The device also includes two latches. The first latch has a first latch output that drives a gate of the p-FET via an inverting circuit element. The second latch has a second latch output that drives a gate of the n-FET via a non-inverting circuit element. The device also includes a reset signal pulse generator that receives the input signal and generates a reset signal pulse in response to a transition in the input signal. Both of the latches are placed in a reset state by the reset signal pulse.