Latch Memory Cell Enables 3D Semiconductor Base Chip Testing
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Solution Overview
Problem
Conventional 3D semiconductor apparatuses face challenges in testing the reliability of base chips without memory cell arrays, as they cannot be tested independently before being stacked with core chips, leading to increased manufacturing costs due to potential defects only being detected after packaging.
Innovation Solution
Incorporating a latch memory cell electrically coupled with through vias, allowing the base chip to be tested even without a memory cell array, by enabling signal transmission and storage, both before and after stacking with other chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a base chip without memory cell array is used in 3D semiconductor apparatus, then device integration is improved, but testing capability deteriorates
Solution Approach 1:
The invention segments the testing function from the memory cell array by introducing a dedicated latch memory cell that is electrically coupled with through vias. This latch memory cell can be independently tested using test equipment, separating the testing requirement from the main memory array structure and enabling reliable testing of base chips without memory cell arrays.
Solution Approach 2:
The latch memory cell acts as an intermediary element between the through vias and the test equipment. It receives signals from test equipment through the through vias, stores test data, and outputs stored data back through the through vias, thereby enabling the testing of base chips that would otherwise lack testing capability.
2Ease of manufacture
If base chip testing is performed after stacking and packaging, then manufacturing process is simplified, but defect detection efficiency deteriorates
Solution Approach 1:
The invention enables preliminary testing of base chips at the wafer level before stacking and packaging by providing a latch memory cell that can be tested independently. This preliminary action allows defects to be detected early in the manufacturing process, before final assembly, improving defect detection efficiency without significantly complicating the manufacturing process.
Data Source
AI summary
A semiconductor apparatus having a through via to be electrically coupled with a chip includes a latch memory cell configured to be electrically coupled with the through via and receive a signal transmitted through the through via, and output a stored signal to the through via.