Latch-Based Memory Array Parallel Read Architecture
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Solution Overview
Problem
Existing memory arrays, such as SRAM, face inefficiencies in read operations due to shared bit lines for writing and reading, limiting simultaneous read capabilities and requiring time-consuming global resets, and complex testing processes.
Innovation Solution
A memory array design featuring memory cells with cross-coupled inverters, transistors, and buffers that allow independent data output connections, enabling parallel read operations and simplified testing through a test chain configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If common bit lines are used for writing and reading in SRAM arrays, then device complexity is reduced, but read speed deteriorates due to charging and discharging requirements
Solution Approach 1:
The patent divides the memory array into multiple independently readable columns, allowing parallel read operations. Each column can be read simultaneously through dedicated output paths, eliminating the speed bottleneck of shared bit lines while maintaining overall device compactness.
Solution Approach 2:
The patent introduces independent column selection capability, adding a dimensional aspect to the memory architecture. This allows simultaneous access to multiple columns that were previously serialized, thereby improving read speed without proportionally increasing device complexity.
2Productivity
If common bit lines are shared for reading, then only one memory cell per column can be read at a time, but providing dedicated bit lines for each cell would increase device complexity
Solution Approach 1:
The patent makes column selection lines multi-functional, allowing them to serve both single-cell selection and multi-cell parallel read operations. This universal approach enables simultaneous reading of multiple cells across different columns without requiring dedicated bit lines for each cell.
Solution Approach 2:
The patent merges the functionality of multiple read operations into a unified architecture where multiple columns can be accessed simultaneously through shared output infrastructure. This combining approach increases productivity while controlling device complexity through resource sharing.
3Device complexity
If global reset requires addressing each word line in turn, then device complexity is reduced, but reset time increases significantly
Solution Approach 1:
The patent implements a global reset mechanism that can simultaneously affect multiple or all word lines at once, rather than requiring sequential addressing. This preliminary action approach allows the reset operation to be performed in advance or in parallel, dramatically reducing reset time while maintaining relatively simple device architecture.
4Device complexity
If testing involves write and read operations to each memory cell in turn, then device complexity is reduced, but testing speed and complexity increase
Solution Approach 1:
The patent segments the testing process to allow parallel testing of multiple memory cells across different columns. By dividing the test operations into independent column-based units, multiple cells can be tested simultaneously, improving testing speed without requiring overly complex test infrastructure.
Solution Approach 2:
The patent changes the testing parameters by enabling simultaneous test operations across multiple columns rather than sequential cell-by-cell testing. This parameter change in the testing approach improves productivity while keeping device complexity manageable through the use of existing memory structure.
Data Source
AI summary
The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.