Latch-Based Memory Row Write Clock for Partial Scan Fault Detection
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Solution Overview
Problem
In latch-based memory arrays, partial scan chains fail to detect reset faults in un-scanned rows due to excessive die area requirements for comprehensive scan paths, leaving many slave latches with undetectable faults.
Innovation Solution
A master/slave latch-based memory design where each row's slave latches are clocked and reset through a row write clock, allowing detection of stuck-at-zero faults via a partial scan chain by using a final column of flip-flops, eliminating the need for direct reset inputs on slave latches and reducing die area demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a comprehensive scan path is implemented through all rows and columns, then fault detection capability is improved, but die area is excessively increased
Solution Approach 1:
The memory array is segmented into scanned rows and unscanned rows. The scan chain is applied only to specific rows (first and last rows) rather than all rows, dividing the testing function into segments that can be managed with limited scan resources while still achieving comprehensive fault detection through the row write clock mechanism.
Solution Approach 2:
The row write clock signal serves multiple functions: it clocks the slave latches during normal operation and simultaneously serves as a test signal for detecting stuck-at-zero faults in unscanned rows. This multi-functionality allows the same signal to be used for both operational control and fault detection, eliminating the need for separate test signals that would increase die area.
2Area of stationary object
If a partial scan chain is used to reduce die area, then die area is reduced, but reset faults in un-scanned rows become undetectable
Solution Approach 1:
The row write clock acts as an intermediary signal that connects the scanned rows to the unscanned rows. By injecting test patterns through the scan chain in scanned rows and propagating them through the master latches to unscanned rows via the row write clock, the intermediary signal enables indirect observation of faults in unscanned rows without requiring direct scan access to those rows.
Solution Approach 2:
The system uses feedback through the row write clock signal to detect faults in unscanned rows. When a stuck-at-zero fault occurs in the row write clock of an unscanned row, the expected clock transitions do not occur, and this abnormality is detected by monitoring the behavior of slave latches in that row, providing feedback about the fault condition.
3Adaptability or versatility
If direct reset inputs are added to slave latches for Universal Asynchronous Reset compliance, then reset functionality is improved, but die area and device complexity are increased
Solution Approach 1:
The reset function is merged with the existing row write clock signal. Instead of adding separate reset inputs to slave latches, the invention combines the reset functionality with the clock signal by controlling the clock gating circuit to hold the row write clock in the inactive state during reset operations. This merging eliminates the need for additional reset circuitry while achieving UAR compliance.
Solution Approach 2:
The slave latches use the existing row write clock signal to service their own reset requirements. By controlling when the row write clock is active or inactive through the clock gating circuit, the system enables slave latches to self-reset without requiring external reset inputs, as the clock signal itself carries the reset control information.
Data Source
AI summary
A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.