Latch-Based Memory Scan Chain for Low-Cost Array Testing
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Solution Overview
Problem
Conventional scan chains for testing integrated circuits are expensive due to the use of scannable flip-flops, making it impractical for large memory arrays on commercial system-on-a-chip (SoC) or processor ICs.
Innovation Solution
The development of latch-based scan chains that use a sequence generator to produce non-overlapping scan sub-clock pulses, allowing data to ripple through the chain one position at a time, thereby enabling low-cost scanning of large memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan chains use scannable flip-flops, then scanning capability is achieved, but cost increases significantly
Solution Approach 1:
The patent replaces expensive scannable flip-flops with inexpensive latches that can be easily manufactured. Latches are simpler memory elements that, when used in a scan chain configuration with non-overlapping clock pulses, provide the necessary scanning capability at a fraction of the cost of conventional flip-flop-based scan chains.
Solution Approach 2:
The patent changes the clocking parameter from overlapping (conventional flip-flop operation) to non-overlapping pulses. This parameter change enables latches to function as scan elements without requiring the complex circuitry of scannable flip-flops, thereby reducing cost while maintaining scanning capability.
2Ease of manufacture
If latch-based scan chains use non-overlapping sub-clock pulses, then cost is reduced, but data rippling speed may be affected
Solution Approach 1:
The patent employs periodic non-overlapping sub-clock pulses to drive data through the latch-based scan chain. Each latch is activated by a specific phase of the periodic clock sequence, enabling systematic data propagation through all latches in the chain while maintaining cost effectiveness.
Solution Approach 2:
The clock signal is segmented into multiple non-overlapping phases, with each phase controlling specific latches in the scan chain. This segmentation allows data to ripple through the chain in a controlled manner, balancing speed requirements with the simplicity and low cost of latch-based implementation.
Data Source
AI summary
An array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.