Latch-Based Memory Self-Testing via Shift Register Chain
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Solution Overview
Problem
The testing of latch-based memory devices is complex and costly due to the inefficiencies of conventional scan test methods, which require significant programming effort and additional hardware, leading to increased power loss and space requirements.
Innovation Solution
A method and device configuration that allows latch-based memory devices to be tested using a shift register chain, where latches are serially connected and controlled by complementary clock signals, enabling simple hardware extensions for test modes without the need for additional MBIST hardware, allowing for efficient testing using classical ATPG approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan test methods are used for latch-based memory devices, then testing can be performed, but testing complexity and cost increase significantly
Solution Approach 1:
The latch-based memory device tests itself by utilizing its own latches configured as a shift register chain. The device's internal latches are reconfigured to form a self-testing mechanism where the memory device serves as both the object under test and the testing apparatus, eliminating the need for external complex test equipment and reducing testing complexity.
Solution Approach 2:
The latches are dynamically reconfigured between functional mode and test mode. During test mode, the latches are serially connected to form a shift register chain, allowing the device to adapt its internal structure for self-testing purposes. This dynamic reconfiguration enables the same hardware to serve multiple functions without adding permanent test-specific structures.
2Productivity
If additional MBIST hardware is implemented, then testing efficiency improves, but device space and power consumption increase
Solution Approach 1:
The existing latches in the latch-based memory device are made multi-functional by enabling them to operate both as functional storage elements during normal operation and as shift register elements during test mode. This universal usage of existing hardware components eliminates the need for separate dedicated test hardware, thereby maintaining testing efficiency without consuming additional device space.
3Productivity
If additional MBIST hardware is implemented, then testing efficiency improves, but power consumption increases
Solution Approach 1:
The memory device performs self-testing using its own operational latches without requiring separate power-hungry MBIST circuits. By reconfiguring existing functional elements for self-diagnosis, the solution achieves efficient testing while minimizing additional power consumption, as no extra dedicated test hardware needs to be powered.
4Reliability
If functional bit patterns are used for testing, then testing can be performed, but programming effort and administrative effort increase
Solution Approach 1:
The device automatically generates and processes test patterns through its shift register chain configuration. The self-testing mechanism eliminates the need for external programming of functional bit patterns and automated generation of test sequences, as the device autonomously performs the testing process using its reconfigured latches.
Solution Approach 2:
The manual process of creating and managing functional bit patterns is replaced by an automated shift register-based testing mechanism. The systematic sequential operation of the shift register chain automatically generates the necessary test sequences, substituting the manual programming approach with an automated hardware-based solution that reduces programming and administrative effort.
Data Source
AI summary
A method of testing a latch based memory device is disclosed. The latch based memory device includes a number of latches, electrical connections and a circuit environment of the latches. A storage functionality of the latches can be tested during a first test phase while a functionality of the electrical connections and the circuit environment of the latches can be tested during a second test phase.